Software Python 3 Hmmm problems Machine Language How does Python function ? due Mon. 3/9 Assembly Language Hmmm RAM CS 5 this week registers 1-bit memory: flip-flops arithmetic bitwise functions logic gates transistors / switches Hardware CS 5 Python taking Hmmm... Logisim's A computer B "canvas" S literally O T U main memory R … R A registers C C T S 1-bit memory: flip-flops I O P arithmetic N A T bitwise functions H logic gates switches: transistors An example of a happy Things seem to get messy around here… Ripple-Carry Adder... Circuit Optimization? try E85 ! using a genetic algorithm 7 gates 16 gates Perhaps artistically optimized! Optimize for what?! What's inside gates? What's the other half of computation? 1940's Electromechanical "gates" (relays) computers metal plate Signal Spring Output Q External Electro- Power (6v) magnet NOT gate Signal Input, A Which gate is this? External Power (6v) Signal Output Q Input, A Input, B AND NAND OR NOR XOR Which gate is this? AND gate External Power (6v) Signal Output Q Input, A Input, B AND NAND OR NOR XOR The Mark 1 an early, relay-based computer http://www-03.ibm.com/ibm/history/exhibits/markI/markI_reference.html Grace Hopper + Howard Aiken, Harvard ~ 1944 ran at 0.00001 MHz 5 tons Addition: 0.6 seconds 530 miles of wiring Multiplication: 5.7 seconds 765,299 distinct parts! Division: 15.3 seconds The Mark 1 an early, relay-based computer a "modern" relay-based computer https://www.youtube.com/watch?v=-ReqdyCxZ9I http://www-03.ibm.com/ibm/history/exhibits/markI/markI_reference.html Grace Hopper + Howard Aiken, Harvard ~ 1944 ran at 0.00001 MHz 5 tons Addition: 0.6 seconds 530 miles of wiring Multiplication: 5.7 seconds 765,299 distinct parts! Division: 15.3 seconds Today's gates? https://www.youtube.com/watch?v=Fxv3JoS1uY8 Silicon-based switches (transistors) a single etched transistor labeled with base (b), emitter (e), and collector (c) Transistors Radio Shack transistors Transistors are current switches: +5v voltage here switch-off-type (pmos) 0v 5v 0v "opens" this wire 5v "cuts" this wire allows current here switch-on-type (nmos) 0v 5v 20 nm 0v "cuts" this wire 5v "opens" this wire switch-on-type transistor single-electron tunneling, or SET transistor Building a NOT gate Transistors are current switches: NOT input output switch-off-type (pmos) 0v 5v Building a NOT gate from transistors… 0v "opens" this wire 5v "cuts" this wire POWER +5 v switch-on-type (nmos) 0v 5v (1 or 0) (0 or 1) OUTPUT INPUT 0v "cuts" this wire 5v "opens" this wire Ground = 0v NOT gate Implemented! Transistors are current switches: switch-off-type (pmos) 0v 5v 0v "opens" this wire 5v "cuts" this wire +5 v POWER switch-on-type (nmos) 0v 5v (1 or 0) (0 or 1) OUTPUT INPUT 0v "cuts" this wire 5v "opens" this wire Ground = 0v Half a computer: the CPU transistors gates arithmetic 6 x 7… ! What's inside gates? What's the other half of computation? Make no mistake… computers process numbers - not symbols. We can only automate what we can arithmetize. 1% - Alan Perlis 99% (communications) Store + Retrievetransport! True! But it misses 99% of what computers do! What? • The circuit starts with R being 0 + S being 0 the "loopback wire" Memory! and Q starts at _0_ from S to R will be 1 • What if S stays 0 and R is set to 1? Q is then set to __ 0 • What happens if S stays 0 and R is set back to 0? "Set" 1 Q still stays (!) at __ S NOR • What happens if R is 0 and S is set to 1? Q is then set to __ • What happens if S is 0 and R is set back to 0? Q still stays (!) at __ 0 NOR Q "Reset" 0 Why does "S" stand for "Set" and R for "Reset" ? R Q is a single S "sets" Q to 1; R "resets" it back to 0. bit of storage Take a look at this circuit: The D (data) line holds a single bit we want to store "we are ready (either a 0 or a 1). to handle the data" How does the strobe bit help store the bit D into Q? Hint: What happens when the "strobe" is 1? • The circuit starts with R being 0 + S being 0 the "loopback wire" Memory! and Q starts at _0_ from S to R will be 1 • What if S stays 0 and R is set to 1? Q is then set to _0_ 1 • What happens if S stays 0 and R is set back to 0? "Set" NOR 0 Q still stays (!) at _0_ S • What happens if R is 0 and S is set to 1? Q is then set to _1_ • What happens if S is 0 and R is set back to 0? 1 Q still stays (!) at _1_ NOR Q "Reset" 0 Why does "S" stand for "Set" and R for "Reset" ? R Q is a single S "sets" Q to 1; R "resets" it back to 0. bit of storage Take a look at this circuit: The D (data) line holds a single bit we want to store "we are ready (either a 0 or a 1). to handle the data" How does the strobe bit help store the bit D into Q? Hint: What happens when the "strobe" is 1? The flip-flop D data inputs AND "strobe" NOR "we are ready to handle the data" NOR AND Q Q is 1 bit of storage D the flip-flop's diagram Q strobe 1 bit of memory! The flip-flop D data inputs AND "strobe" NOR NOR Q But there's a LOT more AND Q is 1 bit than 1 bit of memory… !of storage D the flip-flop's diagram Q strobe 1 bit of memory! Random Access Memory 4 3 2 2 5 1 3 data input bits 6 0 Inputs Simplified values memory Prototype for locations 2 data address bits Accessing write enable line Memory Outputs read enable line 12 bits of RAM 3 data output bits 3 bits stored at location 00 3 bits stored at location 01 3 bits stored at location 10 3 bits stored at location 11 Stacking up Bits of Memory… Speaking of data… Some memory is more equal than others… Registers Main Memory Disk Drive on the Central Processing Unit (replaceable RAM) magnetic storage 8 flip-flops are an 8-bit register D Q D Q D Q D Q D Q D Q D Q D Q s s s s s s s s 100 Registers of 64 bits each 10 GB memory 4 TB drive ~ 10,000 bits ~ 100 billion bits ~ 42 trillion bits (or more) memory from "Leaky Bucket" remagnetizing logic gates capacitors surfaces "640K ought to be enough for anybody" - Bill Gates (contested) Some memory is more equal than others… Registers Main Memory Disk Drive on the Central Processing Unit (replaceable RAM) magnetic storage 8 flip-flops are an 8-bit register D Q D Q D Q D Q D Q D Q D Q D Q s s s s s s s s 100 Registers of 64 bits each 10 GB memory 4 TB drive ~ 10,000 bits ~ 100 billion bits ~ 42 trillion bits (or more) Price ~$100 ~$100 ~$100 7 Time 1 clock cycle 100 cycles 10 cycles 10-9 sec 10-7 sec 10-2 sec If a clock cycle == 1 minute 1 min 1.5 hours 19 YEARS Some memory is more equal than others… Registers Main Memory Disk Drive on the Central Processing Unit (replaceable RAM) magnetic storage 8 flip-flops are an 8-bit register D Q D Q D Q D Q D Q D Q D Q D Q s s s s s s s s 100 Registers of 64 bits each 10 GB memory 4 TB drive ~ 10,000 bits ~ 100 billion bits ~ 42 trillion bits (or more) programs are running Pricefetched and ~$100 programs ~$100 "Off" data is ~$100 saved way executed 1 are stored 7 Time 1 clock cycle 100 cycles 10out here...cycles instruction at a 10-9 sec 10here…-7 sec 10-2 sec time here… If a clock cycle == 1 minute 1 min 1.5 hours 19 YEARS How do we execute sequences of operations? processor CPU stores all instructions and almost all data the instruction's RAM live memory bits select which circuit to use… sends next instruction to the CPU … divider runs 1 instruction memory and sends back locations results for storage, (RAM) if requested… multiplier sends next instruction to the CPU … Jon V.N. 70 years ago… processing fetch stored program CPU execute RAM central processing unit registers random access memory locations limited, fast registers larger, slower memory + arithmetic + no computation Jon V.N. 70 years later… processing fetch stored program CPU execute RAM central processing unit registers random access memory locations limited, fast registers larger, slower memory + arithmetic + no computation Von Neumann Architecture processing program Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations r1 0 0000 0001 0000 0001 General-purpose register, r1 1 1000 0010 0001 0001 2 0110 0010 0010 0001 r2 General-purpose register, r2 3 0000 0010 0000 0010 4 0000 0000 0000 0000 Programs are stored 5 6 (all bits) in memory in machine language Von Neumann Architecture processing program Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations r1 the read instruction 0 0000 0001 0000 0001 General-purpose register, r1 1 1000 0010 0001 0001 2 0110 0010 0010 0001 r2 read r1 General-purpose register, r2 3 0000 0010mul 0000 r2 0010 r1 r1 4 0000 0000add 0000 r2 0000 r2 r1 5 write r2 (all bits) Programs are shown 6 halt in assembly language "mnemonics" instead of bits Von Neumann Architecture processing program Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations r1 0 0000 0001 0000 0001 General-purpose register,the r1 mul instruction 1 1000 0010 0001 0001 2 0110 0010 0010 0001 r2 read r1 General-purpose register, r2 3 0000 0010mul 0000 r2 0010 r1 r1 4 0000 0000add 0000 r2 0000 r2 r1 5 write r2 (all bits) Programs are shown 6 halt in assembly language "mnemonics" instead of bits Von Neumann Architecture processing program Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations r1 0 read r1 General-purpose register, r1 1 mul r2 r1 r1 2 r2 add r2 r2 r1 General-purpose register, r2 3 write r2 4 halt 5 Assembly language "mnemonics" 6 is human-readable instead of bits Human readable? machine language I doubt it! (input) Example #1: Screen 6 Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations 6 0 r1 read r1 General-purpose register r1 1 mul r2 r1 r1 r2 2 General-purpose register r2 add r2 r2 r1 3 write r2 4 halt Hmmm: Harvey mudd miniature machine Von Neumann CPU bottleneck RAM central processing unit registers random access memory locations 0 r1 read r1 General-purpose register r1 1 mul r2 r1 r1 r2 2 General-purpose register r2 add r2 r2 r1 256256 memory memory 16 registers 3 writelocationslocations r2 4 halt vs.