INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION EMERGING RESEARCH DEVICES THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 TABLE OF CONTENTS Scope 1 Difficult Challenges 2 Introduction...................................................................................................................................................2 Device Technologies....................................................................................................................................2 Materials Technologies ................................................................................................................................3 Nano-information Processing Taxonomy.........................................................................................3 Emerging Research Devices ...........................................................................................................4 Memory Taxonomy and Devices..................................................................................................................4 Memory Taxonomy .................................................................................................................................................5 Memory Devices .....................................................................................................................................................5 Logic and Alternative Information Processing Devices................................................................................8 Logic Devices ....................................................................................................................................................... 10 Non-FET, Non Charge-based “Beyond CMOS” Devices ...................................................................................... 17 Emerging Research Architectures.................................................................................................20 Introduction.................................................................................................................................................20 Logic Architecture Benchmarking ..............................................................................................................20 Architectural requirements for a competitive logic device ..................................................................................... 21 Architecture Assessment Methodology................................................................................................................. 21 Observations......................................................................................................................................................... 21 Quantitative Results.............................................................................................................................................. 22 Accelerators in the Future Logic Architecture Landscape..................................................................................... 23 Emerging Research Memory Architectures ...............................................................................................23 Introduction ........................................................................................................................................................... 23 Challenges in Memory Systems ........................................................................................................................... 23 Opportunities for Architectural Exploitation of Emerging Memory Devices ........................................................... 24 Research Needs ................................................................................................................................................... 24 Inference Computing..................................................................................................................................25 Introduction ........................................................................................................................................................... 25 Architecture for Inference...................................................................................................................................... 25 Architecture........................................................................................................................................................... 26 Algorithm Characteristics for Bayesian Inference ................................................................................................. 26 Performance Limits of Information Processing Architectures ....................................................................26 Emerging Memory and Logic Devices—A Critical Assessment ....................................................27 Introduction.................................................................................................................................................27 Technologies beyond CMOS .....................................................................................................................27 Overall Technology Requirements and Relevance Criteria .................................................................................. 27 Electronic Charge-based Nanoscale Devices....................................................................................................... 28 Alternate Computational-State-Variable Nanoscale Devices................................................................................ 29 Potential Performance Assessment for Memory and Logic Devices .........................................................29 Methodology ......................................................................................................................................................... 29 Results.................................................................................................................................................................. 31 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 Fundamental Guiding Principles— “Beyond CMOS” Information Processing ...............................41 Introduction.................................................................................................................................................41 Grand Challenges ......................................................................................................................................41 Computational State Variable(s) other than Solely Electron Charge .................................................................... 41 Non-thermal Equilibrium Systems......................................................................................................................... 41 Novel Energy Transfer Interactions ...................................................................................................................... 41 Nanoscale Thermal Management......................................................................................................................... 41 Sub-lithographic Manufacturing Process .............................................................................................................. 41 Alternative Architectures ....................................................................................................................................... 41 Endnotes/References ....................................................................................................................42 LIST OF FIGURES Figure ERD1 A Taxonomy for Emerging Research Information Processing Devices (The technology entries are representative but not comprehensive.)..............4 Figure ERD2 Exemplary Design Space for a NAND2 Circuit with Fan-out of 1 in Various New Emerging Research Switches. Red points are charge based; other points are examples of switches using other state variables ...................................22 Figure ERD3a-d Technology Performance Evaluation for a) STT MRAM, b) Nanothermal Memory, c) Nanoionic Memory, and d) Ferroelectric Memory.......................34 Figure ERD3e-h Technology Performance Evaluation for e) Electronic Effects Memory, f) Nanomechanical Memory, g) Macromolecular Memory, and h) Molecular Memory..........................................................................................................35 Figure ERD4a-d Technology Performance Evaluation for a) Unconventional Geometry MOSFETs, b) CNT MOSFETs, c) Nanowire, and d) Ge MOSFETs..............36 Figure ERD4e-h Technology Performance Evaluation for e) Tunnel MOSFETs, f) III-V Compound Semiconductor MOSFETs, g) GNR MOSFETs, and h) I MOSFETs.........................................................................................37 Figure ERD4i-l Technology Performance Evaluation for i) Negative Cg FETs, j) Atomic Switches, k) Spin Transistors, and l) NEMS Devices. ...................................38 Figure ERD4m-p Technology Performance Evaluation for m) Pseudospintronic Devices, n) SETs, o) Molecular Switches, and p) Spin Wave Devices. ...........................39 Figure ERD4q-r Technology Performance Evaluation for q) Nanomagnetic Devices, and r) Moving Domain Wall Devices.....................................................................40