Pin Information for the Intel® Stratix®10 1SG10M Device Version: 2020-10-22 TYPE BANK NF74 Package Transceiver I/O 1CU10 28 Transceiver I/O 1CU20 28 Transceiver I/O 1DU10 12 Transceiver I/O 1DU20 12 Transceiver I/O 1EU10 20 Transceiver I/O 1EU20 20 Transceiver I/O 1KU12 28 Transceiver I/O 1KU22 28 Transceiver I/O 1LU12 12 Transceiver I/O 1LU22 12 Transceiver I/O 1MU12 20 Transceiver I/O 1MU22 20 LVDS I/O 2AU1 48 LVDS I/O 2AU2 48 LVDS I/O 2BU1 48 LVDS I/O 2BU2 48 LVDS I/O 2CU1 48 LVDS I/O 2CU2 48 LVDS I/O 2FU1 48 LVDS I/O 2FU2 48 LVDS I/O 2GU1 48 LVDS I/O 2GU2 48 LVDS I/O 2HU1 48 LVDS I/O 2HU2 48 LVDS I/O 2IU1 48 LVDS I/O 2IU2 48 LVDS I/O 2JU1 48 LVDS I/O 2JU2 48 LVDS I/O 2KU1 48 LVDS I/O 2KU2 48 LVDS I/O 2LU1 48 LVDS I/O 2LU2 48 LVDS I/O 2MU1 48 LVDS I/O 2MU2 48 LVDS I/O 2NU1 48 LVDS I/O 2NU2 48 LVDS I/O 3AU1 48 LVDS I/O 3AU2 48 LVDS I/O 3BU1 48 LVDS I/O 3BU2 48 LVDS I/O 3CU1 48 LVDS I/O 3CU2 48 LVDS I/O 3DU1 48 LVDS I/O 3DU2 48 LVDS I/O 3EU1 48 LVDS I/O 3EU2 48 LVDS I/O 3FU1 48 PT- 1SG10M Copyright © 2020 Intel Corp IO Resource Count Page 1 of 49 Pin Information for the Intel® Stratix®10 1SG10M Device Version: 2020-10-22 TYPE BANK NF74 Package LVDS I/O 3FU2 48 LVDS I/O 3GU1 48 LVDS I/O 3GU2 48 LVDS I/O 3HU1 48 LVDS I/O 3HU2 48 LVDS I/O 3IU1 48 LVDS I/O 3IU2 48 LVDS I/O 3JU1 48 LVDS I/O 3JU2 48 LVDS I/O 3KU1 48 LVDS I/O 3KU2 48 LVDS I/O 3LU1 48 LVDS I/O 3LU2 48 SDM shared LVDS I/O SDM_U1 29 SDM shared LVDS I/O SDM_U2 29 3V I/O U10 8 3V I/O U12 8 3V I/O U20 8 3V I/O U22 8 i. Total LVDS channels per bank supporting SERDES Non-DPA and DPA mode is equivalent to (LVDS I/O per bank)/2, inclusive of clock pair. Please refer to Dedicated Tx/Rx Channel column in the pin-out table for the channel availability. ii. Total LVDS channels supporting SERDES Soft-CDR mode is 12 pairs per bank. Please refer to Soft CDR column in the pin out table for the channel availability.