Implementing Bead Probe Technology for In-Circuit Test: A Case Study Mike Farrell Agilent Technologies Loveland, Colorado michael_farrell at agilent dot com Glen Leinbach Caber Contacts, LLC Fort Collins, Colorado glen_leinbach at comcast dot net Copyright © 2007 IEEE. Reprinted from 2007 ITC International Test Conference, Paper 18.1 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Agilent Technologies' products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions at ieee dot org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Implementing Bead Probe Technology for In-Circuit Test: A Case Study Mike Farrell Glen Leinbach Agilent Technologies Caber Contacts, LLC Loveland, Colorado Fort Collins, Colorado michael_farrell at agilent dot com glen_leinbach at comcast dot net 970-679-5526 970-217-1051 and wetting of SAC2 solders. The additional flux Abstract residue left on test points plus the poorer wetting A major OEM implements bead probe technology characteristics of lead-free solder have required the use on a new design to gain test access and coverage of of some best practices to assure reliable probe contact high-speed circuits. Conventional probing techniques at ICT. [Rein05] are incompatible with the density and speed Bare copper (SMOBC-OSP3) test pads and vias requirements of the board. The experiences of a first make unreliable test contacts due to the buildup of implementation of bead probe technology are discussed copper oxide on the surface. The thin copper will not here, including CAD issues at board layout, test fixture prevent board damage during multiple probings. construction and debug, soldering process difficulties, Solder-coated vias are not recommended for probing and test probing problems during the ramp to high- since solder paste applied to them often runs down into volume production. the hole, resulting in the probe contacting either a flux- Introduction filled hole or a flux-covered annular copper ring around the hole. Neither results in reliable contact. A major OEM was developing a high-volume Solid copper test pads covered with reflowed solder graphics board which used DDR21 technology. Product paste, or loaded and soldered through-hole leads, are quality would be assured by a combination of in-circuit the only recommendation for use as test points. test (ICT) and functional test. High-speed busses [Rein06] connecting the two DDR2 memory devices, a DDR2 DIMM connector, and the controller ASIC and other Test Access vs. Test Coverage components could not accommodate conventional ICT Although the terms are often used interchangeably, probe pads due to signal integrity requirements and in this paper “test access” is defined as electrical access layout limitations. This would result in a significant test to a circuit node for testing. “Test coverage” is defined coverage reduction of the board, specifically the DDR2 as the ability to electrically test the board’s section. No test access to the DDR2 section at ICT components. Improving test access is usually a part of meant testing this section at functional test only, improving test coverage, but other factors play a part in complicating component level diagnosis and increasing test coverage. repair costs in manufacturing. On a previous board similar to this design, test Conventional ICT Probing access using conventional probing technology also was The established method of probing boards at ICT not able to test the DDR2 section of the board and has been complicated by the industry’s transition to DIMM connector, resulting in only about 55 percent lead-free processes. Most manufacturers already used a test coverage at ICT through direct and indirect test “no-clean” process, where all solder flux residue is left methods. The DDR2 section of the controlling ASIC on the board covering the solder joints. and the DDR2 memory devices were tested at functional test only. Defects were difficult and Switching to lead-free solder and its higher expensive to isolate. Also, pull-up and pull-down soldering temperatures caused flux breakdown, increas- resistors and capacitors associated with the DDR2 ing solder defect rates such as opens and poor wetting. section could not be tested at functional test. Many manufacturers switched to higher flux content solder pastes to reduce defects by improving the flow 2 Tin(Sn)-silver(Ag)-copper(Cu) lead-free solders 3 Solder Mask On Bare Copper with Organic 1 Double-data-rate two synchronous dynamic random Solderablility Protection: Provides a solderable finish to access memory the PCB pads and through holes. Paper 18.1 INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00©2007 IEEE Alternative test methods such as AOI, X-Ray, and by node name. The test access points information visual inspection were options to increase the test contains the X-Y location, the geometry type coverage of the DDR2 section of the board, but the (through-hole pin, solid pad, via, bead probe), and the OEM wanted to use the existing in-circuit test process side of the board (top or bottom) for the test access if possible and not add another step to the point. This information was instrumental in ensuring manufacturing process. that bead probe access points were limited to nodes in the DDR2 and USB sections. Also, since the bead Implementation probe geometry was identified as a via due to CAD This project was selected by the OEM to conduct an system limitations, it was possible that the test access opportunistic experiment: Implement Agilent Bead location could appear as a possible access point on both Probe Technology (ABPT) [Park04], [Park05] the top and bottom of the board when the CAD was [DoGr06] in the DDR2 section of the board to increase translated. It was imperative to ensure that the test access. The additional test access to previously translation process provided the correct side of the inaccessible nodes should increase the board’s test board on which each bead probe access point was coverage, driving yield improvements at the down- located. Until the translation process was validated, a stream steps of functional test and final assembly. If manual review of the translated data and CAD was yields of this board improved, bead probe technology required to ensure that bead probe test access points would then be implemented on future designs. were assigned to the correct side of the board. In some This product is a high-volume graphics formatter cases, this required modification of the translation board. It uses SMOBC-OSP metallization and is software. assembled in a no-clean lead-free process. Verification Review Board Layout Once the layout of the product was complete, the The first step in the process was to develop a layout CAD was reviewed for the following issues: component (test attribute) for the CAD design system • Verifying that the resulting board_xy file (used to for a bead probe test access point. The designers construct the in-circuit test fixture) contained the worked with Agilent’s bead probe experts to develop a bead probe locations. bead probe test geometry containing the size and shape • Determining which nodes used bead probe test for the apertures in the solder mask and in the solder access points and ensuring that only the DDR2 paste stencil which would be compatible with 4-mil- and USB 2.0 sections of the board used bead wide traces. The resulting geometry was an obround probe test access. opening in the solder mask, providing a test pad 20 mils • long on a 4-mil trace on which to build a bead probe. Ensuring that the resulting board_xy file The OEM’s standard layout rules which had been correctly identified the placement of the bead established for test vias and test pads were used to place probe on either the top or bottom of the board. the bead probe test access points on the board. It was During the test access review, the following prob- jointly decided by the OEM and Agilent to implement lems were discovered: bead probe test access only on the DDR2 section and Layout Driven Problems the USB 2.0 section where it was impractical to place conventional test pads. (Figure 1) • The first problem found was that the bead probe locations were not being translated over to the board_xy file. The problem was that bead probe locations were identified in the CAD data file as vias with a 2-mil pad. The CAD translation has the option of setting the minimum acceptable via pad size. Changing the acceptable via pad size to match the bead probe geometry fixed this problem. • The next problem was related to the first: The bead probe locations were identified as accessible Figure 1: Six bead probe locations on DDR2 bus on from both the top and bottom of the board bare board. because they had been interpreted as vias in the CAD data file. The CAD translation software The layout designer assigned the test attribute to the had an option to only allow test access to the side bead probe locations. The derived files from the CAD of the board identified in the CAD data file for used for test development show the test access points Paper 18.1 INTERNATIONAL TEST CONFERENCE 2 each individual via. Turning on this feature cor- with the same diameter as the probe shaft. The probe rected the problem. face is smooth. The fixture was a dual-well vacuum box • One of the common problems found during the fixture with top and bottom side probing which can test test access review was that some bead probes had four boards at a time.