Chapter 2 Device physics, modeling, and technology for nano-scaled semiconductor devices E. A. Gutie´rrez-D.1,F.Ga´miz2, V. Sverdlov3, S. Selberherr3 and A. Torres-J.1 This chapter introduces the device physics, modeling, and technology for the dif- ferent silicon-based device structures. Quantum-mechanical treatment for the device physics is done as well as the different and alternative approaches for advanced device simulation. The last section takes over the potential use that can be given to new materials and device structures. A preliminary set of applications are reviewed, such as Si-based materials with nanostructured properties, amorphous SiGe alloys applications such as thermal and photodetector sensors. Furthermore, the possibility to make use of CMOS fabrication steps for 3D Si die stacking is also reviewed. 2.1 Bulk MOSFETs and related device structures The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been and still is the workhorse device behind the semiconductor industry. The MOSFET was born in the United States under the fatherhood of Atalla and Kahng in 1960 [2.1], but its birth certificate was issued until 1963 as a patent number 3,102,230 [2.2]. Once the MOSFET showed good and reproducible electrical characteristics, the idea to form a circuit composed of multiple field-effect transistors (FETs) flour- ished with the realization of a commercial integrated circuit (IC) in 1963. Later in 1968 RCA produced the first commercial IC made of 120 p-type FETs as a 20-bit shift register [2.3]. Later in 1968 RCA produced the first commercial com- plementary metal-oxide-semiconductor (CMOS) IC, the 4000 series of CMOS logic gates [2.4]. Of course the concept of the IC is attributed to Jack Kilby who in 1958 patented the idea [2.5], and later in 2000 was granted the Nobel Prize. In 1963 Wanlass and Sah also introduced [2.6], in an experimental way, a set of CMOS logical gates, flip-flops, and ring oscillator with a maximum operating voltage of 40 V. 1National Institute for Astrophysics, Optics and Electronics, INAOE, Puebla, Mexico 2Department of Electronics, University of Granada, Spain 3Institute for Microelectronics, Technical University Vienna, Austria 18 Nano-scaled semiconductor devices À4 This technology showed a transconductance gm ¼ 5 Â 10 A/V, and a leakage current for a single inverter that would amount to 1 W of standby power for 107 inverters, which is about 100 nW per inverter, or 2.5 nA leakage current per inverter. The propagation delay time is about 100 ns. While today a 28 nm CMOS technology, À3 for instance, can have a gm ¼ 7 Â 10 A/V, and a delay time in the order of ps. In the two following sections a description of the conventional FET physics and its limitations will be introduced, and then alternative FET-related structures that alleviate the limited electrical performance of traditional FET devices are introduced in the second section. In the subsequent sections advanced FET-related devices, quantum effects, different approaches for semiconductor modeling and simulation, alternative materials and device structures, are reviewed. 2.1.1 Conventional field-effect transistor (FET) physics and limitations As already mentioned the MOSFET concept was demonstrated in early 1960s based on the surface semiconductor charge controlled by the electric field as shown in Figure 2.1. The charge Qs at the semiconductor surface, close to the semiconductor–gate oxide interface, is controlled by the electric field Ey in the y-axis as shown at the right side, which in turn is controlled by the gate (G) voltage. However, when a potential difference between the drain (D) and source (S) electrodes increases (in the x-axis direction), the charge Qs becomes dependent of both electric field com- ponents, Ey and Ex. Basically what we have is a cloud of charges, either electrons or holes, that modulates the drain-source conductance controlled by the four potentials VG, VS, VD, and VB. In a conventional MOSFET of the 1980s–1990s, with a typical channel length L from 10 to 0.5 mm, a gate oxide Tox from some 60 nm down to 14 nm, the electrical characteristics are like those depicted in Figure 2.2. Both are conventional, non-LDD, polysilicon gate technologies, with a SiO2 gate oxide. These are well-behaved MOSFETs with electrical characteristics close to the ideal behavior for non-low-voltage analog applications. The 10 mm transistor has been fabricated with an experimental process at INAOE [2.7], while the 0.5 mm Inversion channel Gate oxide Tox S G D Qs n+ n+ Depletion Neutral body y P-type semiconductor bulk B Figure 2.1 A conventional n-type MOSFET device Device physics, modeling, and technology for nano-scaled semiconductor 19 240 NFET 120 NFET (W/L) = (100 μm/50 μm) (W/L) = (70 μm/70 μm) 10 μm technology 200 0.5 μm technology 100 T = 60 nm ox Tox = 14 nm (μA) (μA) 160 d d I I 80 120 60 80 40 Channel current, Channel current, 20 40 0 0 012345 0 0.5 1 1.5 2 2.5 3 (a)Vd (V) (b) Vd (V) 8 1 60 2 10 μm technology 0.5 μm technology V = 0.1 V 7 V = 0.1 V d d 50 0 6 0 ) (A) ) (μA) d d I (A) (μA) 40 I d I d 5 I −1 −2 4 S = 152 mV/dec 30 S = 92 mV/dec 3 −2 20 −6 −4 Channel current, current, Channel g = 2.1 × 10 A/V −5 2 m current, Channel gm = 2.88 × 10 A/V Channel current, log ( −3 Channel current, log ( 10 1 V = 0.85 V t Vt = 0.73 V −6 0 −4 0 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 3 (c) Vg (V) (d) Vg (V) Figure 2.2 Electrical characteristics of two conventional MOSFET technologies of 10 mm and 0.5 mm. Plots (a) and (b) have Vg as a parameter from low to high values, while plots (c) and (d) correspond to Id–Vg characteristics in both log and linear scales transistor is from a commercial AMI technology [2.8]. From the Id–Vd character- istics a desirable high output resistance is observed for the 0.5 mm technology. In both cases the saturation, or high output resistance region (a and b), is well defined. The subthreshold regime (c and d) in both cases is also well defined. The 0.5 mm transistor, because of the thinner gate oxide, has a larger current drive capability than that of the 10 mm technology. The subthreshold slope S, a speed-switching feature, is smaller for a 10 mm technology, while the threshold voltage Vt is smaller for the 0.5 mm technology with respect to that of 10 mm. Smaller transistors with advanced technology features, such as thinner gate oxide, show better performance, faster switching, smaller threshold voltage Vt, higher current drive capability, and higher transconductance gm (@Id/@Vg), which result in lower bias voltage, faster circuits, and larger transistor density integration. The device physics and technology behind the enhanced electrical performance, as well as the limitations for a further down scaling, are described as follows. At the semiconductor–oxide interface the energy bands bend as shown in Figure 2.3. 20 Nano-scaled semiconductor devices Oxide y = y Neutral region d Depletion region Ec Tox Ei ψb ψs Gate EF Ev Semiconductor y = yinv y y = 0 Figure 2.3 Energy band bending at the semiconductor–oxide interface for a p-type semiconductor case Several features are observed, which are fundamental for the electrical per- formance of a MOSFET. Under the influence of a positive potential Vg applied to the gate terminal, the energy bands, Ec and Ev, bend down at the semiconductor- oxide interface. The energy band bending produces, in the semiconductor region, a region depleted of holes with an extension yd, and very close the surface, within an extension yinv, an inverted region populated with electrons. Such an inversion layer populated with electrons connects electrically the source with the drain terminal. The conductance of the MOSFET channel depends on both the gate (Vg) and the drain voltage (Vd) in such a way that it produces the electrical characteristics shown in Figure 2.2. A potential barrier at the semiconductor-oxide, and through the gate oxide thickness Tox, develops as well. Such a potential barrier at the oxide prevents electrons from the inversion layer to flow to the gate. However, if the gate oxide Tox is thinner than 10 nm, a considerable amount of electrons can tunnel through the gate oxide to the gate electrode. Another relevant feature is the thickness of the inversion layer yinv, which is in the range within the 10 nm as shown in Figure 2.4. Figure 2.4 shows the simulated current density for an n-type MOSFET with a gate oxide Tox ¼ 14 nm for a particular bias condition Vg ¼ 0.3 V and Vd ¼ 0.1 V. Most of the current that flows from source-to-drain is confined into a well potential of a thickness yinv of about 5 nm. Such a thickness, which determines the channel conductivity, is bias and technology dependent. It is uniform along the channel if the drain-to-source potential is zero. The gate voltage dependence of yinv, the inversion charge n, the surface potential ys, and the channel current Id are shown in Figure 2.5. The inversion channel gets thinner as the Vg voltage increases, while the inversion charge in the channel n increases exponentially, which compensates the thinning of the inversion channel.