Design of RF Silicon on Insulator (SOI) Switches for Ultra Wideband Wireless Communication Applications Y8 BO 6&+22L OF ELECTRICAL & ELECTRONIC ENGINEERING 7 De sign of RF Silicon on Insulator (SOI) Switches for Ultra Wideband Wireless Communication Applications Design of RF Silicon on Insulator (SOI) Switches for Ultra Wideband Wireless Communication Applications YU BO SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfilment of the requirement for the degree of 2017 Doctor of Philosophy 207 Design of RF Silicon on Insulator (SOI) Switches for Ultra Wideband Wireless Communication Applications YU BO YU BO SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfilment of the requirement for the degree of Doctor of Philosophy 207 ACKNOWLEDGEMENTS First and foremost, I wish to thank my supervisors, Professor Yeo Kiat Seng and Professor Ma Kaixue, for their guidance, discussions, suggestions and encouragement throughout the four years of Ph.D. study. It has been my honor to be their Ph.D. student. I would like to thank Singapore Economic Development Board (EDB) for their financial support on this project, and thank GLOBALFOUNDRIES Singapore for giving the chance to take this project. I also wish to express my appreciation to my boss Shaoqiang and Verma in GLOBALFOUNDRIES Singapore for their support and instructions on this research work. In addition, I am grateful to my colleagues, Shyam, Rui Tze and Sun Tao for many helpful discussions. Last but not least, I am thankful to Damien and Kam Chew from GLOBALFOUNDRIES Human Resource L&OD department who made a lot of effort to support the project. I would also like to thank NTU for supporting this research project and my NTU friends and students Fanyi, Wanxin, Kumar, Jiangan and Zouqiong for all their assistance and useful discussions. Special thanks to Fanyi, who rendered much help to me on the circuit design plan and layout, and Wanlan, who helped me in the device measurement. For this thesis, I would like to thank the thesis advisory committee members: Professor Goh Wang Ling and Professor Chen Tupei for their time, interest, and helpful comments. Finally, I would like to thank my wife, Guoying for her encouragement and support throughout my Ph.D. studies. i TABLE OF CONTENTS Chapter 1 Introduction ...................................................................................................... 14 1.1 Motivation ............................................................................................................ 14 1.2 Thesis organization ............................................................................................... 16 Chapter 2 Review of RF switch design ............................................................................. 19 2.1 RF switching block ............................................................................................... 19 2.2 Characteristics and properties of RF switches ....................................................... 20 2.2.1 Insertion loss ........................................................................................ 20 2.2.2 Isolation ............................................................................................... 21 2.2.3 Return loss ........................................................................................... 22 2.2.4 Power handling, 1 dB compression point (P1dB) .................................. 22 2.2.5 Linearity ............................................................................................... 23 2.2.6 Switching speed ................................................................................... 24 2.3 RF switches .......................................................................................................... 24 2.3.1 RF MEMS switch ................................................................................. 24 2.3.2 Solid state switches .............................................................................. 25 2.3.2.1. PIN diode switches ............................................................................. 26 2.3.2.2. FETs switches..................................................................................... 26 2.4 Common switch design techniques ....................................................................... 28 2.4.1 Gate biasing ......................................................................................... 28 2.4.2 Transistor stack .................................................................................... 29 ii 2.4.3 Body floating ....................................................................................... 30 2.4.4 Series-shunt with input/output matching networks ................................ 34 2.4.5 Matching network (MN), λ/4 transmission lines ................................... 35 2.4.6 Traveling-wave concept ....................................................................... 36 Chapter 3 Introduction to SOI........................................................................................... 39 3.1 SOI Benefits ......................................................................................................... 39 3.1.1 Reduction of substrate parasitic capacitances ........................................ 40 3.1.2 Ideal device isolation and smaller layout area ....................................... 41 3.1.3 Latch up elimination ............................................................................. 41 3.2 FD SOI and PD SOI ............................................................................................. 42 3.3 Floating body versus body tied SOI ...................................................................... 43 3.4 HR SOI and HR trap-rich SOI .............................................................................. 44 Chapter 4 Ultra wideband SPST switch design considerations .......................................... 48 4.1 SPST switch topology ........................................................................................... 48 4.1.1 Series only configuration ...................................................................... 48 4.1.2 Series-shunt configuration .................................................................... 52 4.1.3 Series-Shunt with matching network Configuration .............................. 57 4.2 SPST switch device size selection ......................................................................... 60 4.2.1 Simulation on varying matching inductor value .................................... 60 4.2.2 Simulation on varying series transistor width ........................................ 62 4.2.3 Simulation on varying shunt transistor width ........................................ 63 4.3 Summary .............................................................................................................. 66 Chapter 5 Ultra wideband SPDT switch design................................................................. 67 iii 5.1 SOI NMOS schematic and substrate ..................................................................... 67 5.2 Stress memorization technique (SMT) and device characterization ....................... 69 5.3 SOI NMOS Coff model .......................................................................................... 71 5.4 SPDT topology ..................................................................................................... 73 5.5 Simulated and measured results of SPDT switch ................................................... 81 5.5.1 S-parameters ........................................................................................ 82 5.5.2 Power handling and linearity ................................................................ 89 5.5.3 Switch speed ........................................................................................ 92 5.6 Summary and comparison ..................................................................................... 93 Chapter 6 Ultra wideband SP4T switch design ................................................................. 96 6.1 SP4T topology ...................................................................................................... 96 6.2 SP4T switch simulation ........................................................................................ 99 6.3 Measured results of SP4T switch ........................................................................ 102 6.3.1 S-parameters ...................................................................................... 103 6.3.2 Power handling and linearity .............................................................. 107 6.4 Summary and comparison ................................................................................... 109 Chapter 7 Ultra wideband DPDT switch design .............................................................. 112 7.1 Introduction ........................................................................................................ 112 7.2 DPDT switch design considerations .................................................................... 112 7.2.1 DPDT switch configuration ................................................................ 113 7.2.2 DPDT switch size ............................................................................... 116 7.2.3 Switch design with novel recessed device_Gen2 switch ..................... 116 iv 7.2.4 DPDT switch design with through