Circuit Optimisation using Device Layout Motifs Yang Xiao Ph.D. University of York Electronics July 2015 Abstract Circuit designers face great challenges as CMOS devices continue to scale to nano dimensions, in particular, stochastic variability caused by the physical properties of transistors. Stochas- tic variability is an undesired and uncertain component caused by fundamental phenomena associated with device structure evolution, which cannot be avoided during the manufac- turing process. In order to examine the problem of variability at atomic levels, the `Motif ' concept, defined as a set of repeating patterns of fundamental geometrical forms used as design units, is proposed to capture the presence of statistical variability and improve the device/circuit layout regularity. A set of 3D motifs with stochastic variability are investigated and performed by technology computer aided design simulations. The statistical motifs compact model is used to bridge between device technology and circuit design. The statistical variability information is transferred into motifs' compact model in order to facilitate variation-aware circuit designs. The uniform motif compact model extraction is performed by a novel two-step evolutionary algorithm. The proposed extraction method overcomes the drawbacks of conventional extraction methods of poor convergence without good initial conditions and the difficulty of simulating multi-objective optimisations. After uniform motif compact models are obtained, the statistical variability information is injected into these compact models to generate the final motif statistical variability model. The thesis also considers the influence of different choices of motif for each device on cir- cuit performance and its statistical variability characteristics. A set of basic logic gates is constructed using different motif choices. Results show that circuit performance and vari- ability mitigation can benefit from specific motif permutations. A multi-stage optimisation methodology is introduced, in which the processes of optimisation are divided into several stages. Benchmark circuits show the efficacy of the proposed methods. The results presented in this thesis indicate that the proposed methods are able to provide circuit performance improvements and are able to create circuits that are more robust against variability. ii Contents Abstract ii List of Figures vii List of Tables xx Acknowledgments xxiii Declaration xxiv Hypothesis xxv 1 Introduction 1 1.1 Motivation . 1 1.2 Aims and Objectives . 3 1.3 Organisation of The Thesis . 3 2 Transistor Scaling and Variability 6 2.1 Scaling of Transistor Device . 8 2.1.1 Scaling Principle . 8 2.1.2 Scaling Challenges . 10 2.2 Transistor Variability Classification . 15 2.2.1 Random/Stochastic Variation . 15 2.2.2 Systematic Variation . 15 2.3 Sources of Stochastic Variability . 17 2.3.1 Random Dopant Fluctuation . 17 2.3.2 Line Edge Roughness . 19 2.3.3 Interface Roughness . 20 2.3.4 Polysilicon Grain Boundaries . 21 2.4 Impact of Transistor Variability on Device/Circuit Performance and Monte Carlo Simulation . 22 2.4.1 Impact on Delay Time . 23 2.4.2 Impact on Leakage Current . 24 iii Contents iv 2.4.3 Monte Carlo Simulation (Statistical Simulation) . 25 2.5 Summary . 26 3 Motifs Physical Simulation 27 3.1 Device Simulation and Methodology . 28 3.1.1 CMOS Device Fabrication Flow . 28 3.1.2 3D Device Structure Simulation Methodology in TCAD . 32 3.2 Motifs Design Methodology . 42 3.2.1 Layout Consideration and Variability . 42 3.2.2 Motif Concept . 46 3.2.3 Motifs Design . 50 3.3 TCAD Statistical Variability Simulation Methodology . 53 3.3.1 Line Edge Roughness Modelling . 53 3.3.2 TCAD Statistical Simulation Approach . 58 3.4 Experiment Results and Discussion . 59 3.4.1 Motif Verification . 60 3.4.2 Statistical Motif Simulation Results . 63 3.5 Summary . 66 4 Evolutionary Algorithms 77 4.1 What is an Evolutionary Algorithm? . 79 4.2 Operation of an Evolutionary Algorithm . 80 4.2.1 Representation . 80 4.2.2 Selection . 80 4.2.3 Reproduction . 82 4.2.4 Evaluation . 88 4.2.5 Termination Criteria . 88 4.3 Type of Evolutionary Algorithm . 89 4.3.1 Genetic Algorithm . 89 4.3.2 Evolutionary Strategies . 90 4.3.3 Evolutionary Programming . 91 4.3.4 Genetic Programming . 91 4.3.5 Multi-Objective Evolutionary Algorithm (MOEA) . 92 4.4 Evolutionary Algorithm for VLSI Design . 93 4.4.1 Charateristics of Problem Instances . 93 4.4.2 Problem Instances Decomposition . 94 4.4.3 Application of EA on VLSI Design . 94 4.5 Summary . 97 5 Extraction and Modelling Statistical Motifs Compact Model 99 Contents v 5.1 Device Compact Model and Extraction Method . 100 5.1.1 Device Compact Model . 100 5.1.2 Model Extraction and Optimisation Methodology . 108 5.2 Two Step Evolutionary Algorithm Extraction Method . 109 5.2.1 Overview of Two Step Evolutionary Algorithm Model Extraction Method109 5.2.2 Representation . 111 5.2.3 Selection Process . 112 5.2.4 Mutation Process . 112 5.2.5 Motif Netlist Simulation . 113 5.2.6 Fitness Evaluation . 113 5.3 Experiment Results and Analysis . 116 5.3.1 Experiment Setting-up . 116 5.3.2 Reference Device Extraction . 116 5.3.3 O Shaped Device Extraction . 118 5.4 Statistical Device Layout Motif Compact Model Modelling . 122 5.4.1 Direct Statistical Compact Modelling methodology . 122 5.4.2 Statistical Compact Modelling Results and Verification . 126 5.5 Summary . 128 6 Circuit Optimisation using Motifs and Evolutionary Algorithm 130 6.1 Applying Motifs to Basic Logic Gates . 131 6.1.1 Logic Gates Test . 131 6.1.2 Exhaustive Testing . 132 6.1.3 Results and Observations . 133 6.2 Multi-Stage Evolutionary Algorithm for Circuit Optimisation . 145 6.2.1 Methodology . 145 6.2.2 First Stage EA Optimisation . 148 6.2.3 Second Stage EA Optimisation . 151 6.3 Evolutionary Algorithm Verification . 154 6.3.1 Benchmark Circuit I: XOR . 154 6.4 Benchmark Circuits Evaluation . 155 6.4.1 Benchmark Comparison Circuits . 155 6.4.2 Benchmark Circuit II: Half Adder . 159 6.4.3 Benchmark Circuit III: Full Adder . 161 6.5 Summary . 167 7 Conclusions and Future Work 168 7.1 Conclusions . 168 7.2 Summary . 169 7.3 Future Work . 172 Contents vi A NMOS Device TCAD Script 174 B Model Parameters Definition 182 C NMOS reference device netlist 185 Bibliography 186 List of Figures 1.1 A comparison of the transistor counts in various microprocessors, with a curve showing the projected counts following Moore's predictions of a doubling every 24 months [4]. 2 1.2 The thesis organisation diagram, which summaries main chapters' topics, key observations (represented by .) and points of interest (represented by •). 5 2.1 Trends in device electronics. The number of transistor per processor chip has increased (blue star line) as MOSFET device feature size scaling (red dot line). Evolution of MOSFET gate length is represented by filled red circles and ITRS predictions is shown by open red circles [9]. 8 2.2 A cross-sectional structure of scaled MOS device [11]. 9 2.3 Evolution of lithography wavelength (blue line) as silicon feature size (red dot line) scaling. As devices scale to nanometer regions, manufacturability chal- lenges \subwavelength gap" continue to grow. The illumination wavelength (193 nm) is much greater than the feature size (45 nm and below) [14]. 11 2.4 An example of lithography simulation of flip-flop. Because of pattern distor- tion, some of points in the layout are shorted and highlighted by red circle [16]. 12 2.5 The comparison of device layout pattern using OPC or no OPC [17]. The case where OPC correction is used obviously has higher yield than no OPC design. 13 2.6 Threshold voltage Vth roll-off and drain induced barrier lowering (DIBL). Vth decreases as the channel length reduction. In addition to this, Vth further reduced when drain voltage increases is caused by DIBL [25]. 14 2.7 Barrier height lowering due to channel length reduction [8]. 14 vii List of Figures viii 2.8 Random discrete dopant fluctuations illustrated in 3D device structure [22]. It is impossible to perfectly control the exact quantity and position of dopant atom while dopant atoms are being implanted into the silicon. These results in exact differences in the electronic characteristics of two transistors, even both are fabricated under the same conditions. 16 2.9 Line edge roughness (LER) in 3D device structure [22]. The random deviation between actual gate edges and ideal definition of gate edges is not avoided due to the limitation of resolution in optical lithography. LER results in enhanced lateral diffusion and effective channel length reduction. 16 2.10 Poly-silicon grain boundaries (PSG) and gate oxide roughness (TOX) in 3D device structure [22]. PSG is.