2 COMPUTER SYSTEMS ORGANIZATION Central processing unit (CPU) Control unit Arithmetic logical unit (ALU) I/O devices Registers Main … … memory Disk Printer Bus Fig. 2-1. The organization of a simple computer with one CPU and two I/O devices. A + B A Registers B ALU input register A B ALU input bus ALU ALU output register A + B Fig. 2-2. The data path of a typical von Neumann machine. public class Interp { static int PC; // program counter holds address of next instr static int AC; // the accumulator, a register for doing arithmetic static int instr; // a holding register for the current instruction static int instr3type; // the instruction type (opcode) static int data3loc; // the address of the data, or −1 if none static int data; // holds the current operand static boolean run3bit = true; // a bit that can be turned off to halt the ma public static void interpret(int memory[ ], int starting3address) { // This procedure interprets programs for a simple machine with instructions // one memory operand. The machine has a register AC (accumulator), used // arithmetic. The ADD instruction adds an integer in memory to the AC, for e // The interpreter keeps running until the run bit is turned off by the HALT ins // The state of a process running on this machine consists of the memory, the // program counter, the run bit, and the AC. The input parameters consist of // of the memory image and the starting address. PC = starting3address; while (run3bit) { instr = memory[PC]; // fetch next instruction into instr PC = PC + 1; // increment program counter instr3type = get3instr3type(instr); // determine instruction type data3loc = find3data(instr, instr3type);// locate data (−1 if none) if (data3loc >= 0) // if data3loc is −1, there is no operand data = memory[data3loc]; // fetch the data execute(instr3type, data); //execute instruction } } private static int get3instr3type(int addr) { ... } private static int find3data(int instr, int type) { ... } private static void execute(int type, int data){ ... } } Fig. 2-3. An interpreter for a simple computer (written in Java). S1 S2 S3 S4 S5 Instruction Instruction Operand Instruction Write fetch decode fetch execution back unit unit unit unit unit (a) S1: 1 2 3 4 5 6 7 8 9 S2: 1 2 3 4 5 6 7 8 S3: 1 2 3 4 5 6 7 … S4: 1 2 3 4 5 6 S5: 1 2 3 4 5 123456789 Time (b) Fig. 2-4. (a) A five-stage pipeline. (b) The state of each stage as a function of time. Nine clock cycles are illustrated. S1 S2 S3 S4 S5 Instruction Operand Instruction Write decode fetch execution back Instruction unit unit unit unit fetch unit Instruction Operand Instruction Write decode fetch execution back unit unit unit unit Fig. 2-5. (a) Dual five-stage pipelines with a common instruction fetch unit. S4 ALU ALU S1 S2 S3 S5 Instruction Instruction Operand Write fetch decode fetch LOAD back unit unit unit unit STORE Floating point Fig. 2-6. A superscalar processor with five functional units. Control unit Broadcasts instructions 8 × 8 Processor/memory grid Processor Memory Fig. 2-7. An array processor of the ILLIAC IV type. Local memories Shared Shared memory memory CPU CPU CPU CPU CPU CPU CPU CPU Bus Bus (a) (b) Fig. 2-8. (a) A single-bus multiprocessor. (b) A multicomputer with local memories. AddressAddress 1 Cell Address 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 16 bits 7 7 (c) 8 12 bits 9 (b) 10 11 8 bits (a) Fig. 2-9. Three ways of organizing a 96-bit memory. 2222222222222222222222222222222222 22222222222222222222222222222222221 Computer1 Bits/cell 1 1 1 1 12222222222222222222222222222222222Burroughs B17001 1 1 22222222222222222222222222222222221 IBM PC1 8 1 1 1 1 12222222222222222222222222222222222DEC PDP-81 12 1 22222222222222222222222222222222221 IBM 11301 16 1 1 1 1 12222222222222222222222222222222222DEC PDP-151 18 1 12222222222222222222222222222222222XDS 9401 24 1 22222222222222222222222222222222221 Electrologica X81 27 1 1 1 1 12222222222222222222222222222222222XDS Sigma 91 32 1 22222222222222222222222222222222221 Honeywell 61801 36 1 1 1 1 12222222222222222222222222222222222CDC 36001 48 1 22222222222222222222222222222222221 CDC Cyber1 60 1 Fig. 2-10. Number of bits per cell for some historically interesting commercial computers. AddressBig endian Little endian Address 0 0 1 2 3 3 2 1 0 0 4 4 5 6 7 7 6 5 4 4 8 8 9 10 11 11 10 9 8 8 12 12 13 14 15 15 14 13 12 12 Byte Byte 32-bit word 32-bit word (a) (b) Fig. 2-11. (a) Big endian memory. (b) Little endian memory. Transfer from big endian to Transfer and Big endian Little endian little endian swap 0 J I M M I J 0 M I J J0I M 4 S M I T TI M S 4 T I M S S4M I T 8 H 0 0 0 00 0 H 8 0 0 0 H H80 0 0 12 0 0 0 21 00 0 21 12 21 0 0 0 0120 0 21 16 0 0 1 4 00 1 4 16 4 1 0 0 0160 1 4 (a) (b) (c) (d) Fig. 2-12. (a) A personnel record for a big endian machine. (b) The same record for a little endian machine. (c) The result of transferring the record from a big endian to a little endian. (d) The result of byte-swapping (c). 22222222222222222222222222222222222222222222222222222 222222222222222222222222222222222222222222222222222221 Word size1 Check bits1 Total size1 Percent overhead 1 1 1 1 1 1 12222222222222222222222222222222222222222222222222222281 41 121 50 1 222222222222222222222222222222222222222222222222222221 161 51 211 31 1 1 1 1 1 1 122222222222222222222222222222222222222222222222222222321 61 381 19 1 222222222222222222222222222222222222222222222222222221 641 71 711 11 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222222221281 81 1361 6 1 1222222222222222222222222222222222222222222222222222222561 91 2651 4 1 222222222222222222222222222222222222222222222222222221 5121 101 5221 2 1 Fig. 2-13. Number of check bits for a code that can correct a single error. A A A Error 0 0 0 0 1 C C C 1 1 1 1 1 1 11 0 0 0 0 0 Parity bits B B B (a) (b) (c) Fig. 2-14. (a) Encoding of 1100. (b) Even parity added. (c) Error in AC. Memory word 1111000010101110 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Parity bits Fig. 2-15. Construction of the Hamming code for the memory word 1111000010101110 by adding 5 check bits to the 16 data bits. Main memory CPU Cache Bus Fig. 2-16. The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located. 4-MB memory chip Connector Fig. 2-17. A single inline memory module (SIMM) holding 32 MB. Two of the chips control the SIMM. Registers Cache Main memory Magnetic disk Tape Optical disk Fig. 2-18. A five-level memory hierarchy. Intersector gap D or irec ct E tion se C Pream o 1 s ble f ta bit C di 6 da sk 409 r ot 40 a 96 tio da n Read/write ta b e it bl head s am Direction re E P of arm C C motion Width of 1 bit is Disk Track 0.1 to 0.2 microns arm width is 5–10 microns Fig. 2-19. A portion of a disk track. Two sectors are illustrated. Read/write head (1 per surface) Surface 7 Surface 6 Surface 5 Surface 4 Surface 3 Direction of arm motion Surface 2 Surface 1 Surface 0 Fig. 2-20. A disk with four platters. 222222222222222222222222222222222222222222222222222222222222 2222222222222222222222222222222222222222222222222222222222221 Parameters1 LD 5.25′′ 1 HD 5.25′′ 1 LD 3.5′′ 1 HD 3.5′′ 1 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222222222222222Size (inches)1 5.251 5.251 3.51 3.5 1 2222222222222222222222222222222222222222222222222222222222221 Capacity (bytes)1 360K1 1.2M1 720K1 1.44M 1 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222222222222222Tracks1 401 801 801 80 1 2222222222222222222222222222222222222222222222222222222222221 Sectors/track1 91 151 91 18 1 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222222222222222Heads1 21 21 21 2 1 1222222222222222222222222222222222222222222222222222222222222Rotations/min1 3001 3601 3001 300 1 2222222222222222222222222222222222222222222222222222222222221 Data rate (kbps)1 2501 5001 2501 500 1 1 1 1 1 1 1 2222222222222222222222222222222222222222222222222222222222221 Type1 Flexible1 Flexible1 Rigid1 Rigid 1 Fig. 2-21. Characteristics of the four kinds of floppy disks. 222222222222222222222222222222222222222222222222 2122222222222222222222222222222222222222222222222Name1 Data bits1 Bus MHz1 MB/sec 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222SCSI-11 81 51 5 1 2122222222222222222222222222222222222222222222222Fast SCSI1 81 101 10 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222Wide Fast SCSI1 161 101 20 1 2122222222222222222222222222222222222222222222222Ultra SCSI1 81 201 20 1 1 1 1 1 1 1222222222222222222222222222222222222222222222222Wide Ultra SCSI1 161 201 40 1 1222222222222222222222222222222222222222222222222Ultra2 SCSI1 81 401 40 1 2122222222222222222222222222222222222222222222222Wide Ultra2 SCSI1 161 401 80 1 Fig. 2-22. Some of the possible SCSI parameters. Strip 0 Strip 1 Strip 2 Strip 3 (a) Strip 4 Strip 5 Strip 6 Strip 7 RAID level 0 Strip 8 Strip 9 Strip 10 Strip 11 Strip 0 Strip 1 Strip 2 Strip 3 Strip 0 Strip 1 Strip 2 Strip 3 RAID (b) Strip 4 Strip 5 Strip 6 Strip 7 Strip 4 Strip 5 Strip 6 Strip 7 level 1 Strip 8 Strip 9 Strip 10 Strip 11 Strip 8 Strip 9 Strip 10 Strip 11 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (c) RAID level 2 Bit 1 Bit 2 Bit 3 Bit 4 Parity (d) RAID level 3 Strip 0 Strip 1 Strip 2 Strip 3 P0-3 (e) Strip 4 Strip 5 Strip 6 Strip 7 P4-7 RAID level 4 Strip 8 Strip 9 Strip 10 Strip 11 P8-11 Strip 0 Strip 1 Strip 2 Strip 3 P0-3 Strip 4 Strip 5 Strip 6 P4-7 Strip 7 (f) Strip 8 Strip 9 P8-11 Strip 10 Strip 11 RAID level 5 Strip 12 P12-15 Strip 13 Strip 14 Strip 15 P16-19 Strip 16 Strip 17 Strip 18 Strip 19 Fig.