Fundamental performance differences between CMOS and CCD imagers: Part III James Janesick*a, Jeff Pintera, Robert Pottera, Tom Elliottb, James Andrewsc, John Towerc, John Chengd, Jeanne Bishopd a Sarnoff Corporation, 4952 Warner Av., Suite 300, Huntington Beach, CA. 92649 b Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA. 91109 c Sarnoff Corporation, CN5300, 201 Washington Road, Princeton, NJ 08543-5300 dChronicle Technology, 4340 Von Karman Av., Suite 120, Newport Beach, CA. 92660 ABSTRACT This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff. Keywords: CMOS and CCD scientific imagers. 1. INTRODUCTION This paper continues discussions on ‘fundamental performance differences of CMOS and CCD imagers’ stemming from three previous papers delivered on the subject1-3. The papers collectively demonstrate that significant progress has taken place for Scientific CMOS imagers in achieving equal to or better performance than the CCD. High performance implies very low read noise (1 e-), high quantum efficiency (transmission limited), deep depletion for near IR and soft x-ray charge collection efficiency (CCE) performance, low pixel cross-talk (high MTF), high charge transfer efficiency (CTE), 14-16 bit high dynamic range, high signal-to-noise for low contrast scenes and very high speed / low noise parallel readout using integrated designs. This paper is specifically focused on three main development areas; 1). Sandbox fabrication, 2). charge-coupled CMOS pixel development and 3). CMOS pixel MOSFET development. The last section of the paper is devoted to planned future developments of large high performing CMOS imagers for scientific applications. 2. SANDBOX FABRICATION As successfully implemented in fabricating past high performance scientific CCDs, Sarnoff and its customers also rely on ‘Sandbox’ lot runs for CMOS imager development and prototyping purposes4. Multiple customers take part on these runs to share fabrication expenses and team in developing CMOS imager technology together (cost is proportional to the real estate occupied on the silicon wafer). Typically after an imager is developed with Sandbox, efforts for a specific customer are directed to a dedicated lot run in fabricating the production sensor. Sandbox lots are normally fabricated at Jazz Semiconductor using their 0.18µm CMOS process (although some fabrication work also takes place at other CMOS foundries). Sarnoff has also incorporated five custom implants to the base 0.18um process required for high performing CMOS pixels. Also, thick high resistivity epitaxial (epi) silicon and SOI wafers are often used for deep depletion near IR and x-ray imagers. Figure 1 shows an example Sandbox reticule layout currently under test. The design includes six small 496(V) x 512(H) Minimal Arrays,2 one large Minimal Array and a block of test ADCs that all occupy an area of * e-mail: [email protected], Paper Number: 7439A-6, San Diego Aug 2009. approximately 22mm x 22mm. The 1536 x 1536 sensor is based on 8µm ‘five transistor pinned photo diode (5T PPD)’ pixels designed for a SNAP2 frame readout rate of 30 frames/sec. The small Minimal arrays contain 8µm, 16µm and 24µm 3TPPD and 5TPPD pixels and a wealth of development CMOS test pixels including a buried channel CMOSCCD. This particular Sandbox (Sandbox V) used 25 silicon wafers that were split for 3.3V and 5.0V processing. A 5V process allows high voltage operation for improved dynamic range, lower pixel cross-talk, deeper depletion and provides a thicker gate oxide compared to 3.3V processing (3x) to reduce poly gate leakage issues. Sandbox V incorporates many new CMOS features some that are discussed below. Test data from this Sandbox run will be shared in upcoming papers. 3. CMOS PIXEL DEVELOPMENT 3.1 Substrate Bias Sandbox V contains numerous experiments involving substrate bias aimed at maximizing CCE performance. Compared to CCDs, low pixel cross-talk is more difficult to achieve for CMOS especially for thick imagers that detect near IR and x-ray photons. For these sensors high resistivity epi silicon is an absolute requirement for deep depletion and good CCE. However, even when silicon is fully depleted, the desired low cross-talk may not be realized. Hence, an additional bias voltage across the imager called substrate bias is the only means to deal with the problem (other than just increasing pixel size). Following how very deep depletion CCDs handled the CCE problem,5 substrate bias can also significantly improve cross-talk performance for CMOS imagers. However, the technique is considerably more difficult to implement compared to CCDs, and therefore, is considered a ‘custom’ feature for any design attempted. Discussions below will only brief the reader on a few important aspects behind substrate bias inner workings leaving most technical details for another paper. Figure 2 illustrates a cross-section of CMOS imager showing the substrate bias contact, pixels and drivers for the pixels. It is important to note that it is just not enough to simply deplete the entire structure with substrate bias. But in addition, a sufficient potential barrier must be realized between the pixel grounded p-wells and the bias to prevent (hole) leakage current flow. The required barrier height is primarily dependent on the positive bias potential applied on adjacent n+ regions (e.g., pixel photo diode) and the dimensions of the p-well and pixel photo diode. Figure 3a presents a PISCES (Poisson and Current Continuity Equation Solver) / SUPREM (Stanford University Process Modeling) simulation that plots potential through the pixel’s p-well region as a function of device depth. Photo diode bias is varied (0.4, 0.8, 1.2 and 1.6V). Note as the diode bias decreases the barrier height under the p-well also decreases signifying a limit to the amount of substrate bias that can be applied. To prevent leakage current from flowing, at least 500mV of barrier is usually required (i.e., 20kT). Figure 3b plots substrate current and bias showing where that limit occurs. It should be mentioned that barrier height also decreases with silicon resistivity and increases with its thickness. Also, the width of the pixel p-well requires minimum design rules but not too small to cause pixel-to-pixel blooming. The photo diode should have the largest active fill factor possible for maximum substrate bias. As seen in Fig 2, digital logic elements contained on the imager (e.g., address encoders, pixel bipolar drivers, multiplexers, etc.) also rely on grounded p-wells for operation. It is not possible to ‘pinch off’ this circuitry from substrate bias as is done for the pixels. Instead a biased deep n-well implant is employed under these circuits to generate a sufficient barrier for substrate bias. The figure also shows that the substrate bias contact is far removed from the pixels. As it turns out, the pixel depletion region does not extend to the backside of the sensor if the depletion reaches the substrate contact first. The minimum separation dimension between the pixels and the substrate contact assumes that this distance is approximately equal to the thickness of the silicon. CCE improvements using substrate bias are discussed in the next section. 3.2 Pixel Cross-talk The other challenge for CMOS imagers to achieving good CCE performance is minimizing the transit time in moving signal charge to the target pixel’s collection region without significant diffusion among its neighbors. For example, Fig. 4a illustrates how a charge packet travels from the backside of the imager to the frontside by the electric field generated by the pixel and substrate bias. Figure 4b plots the potential versus depth as the substrate voltage changes from 0 to - 20V. The slope of these curves represents the field strength that increases with substrate bias. During transit, thermal diffusion takes place increasing the charge cloud size following a Gaussian distribution of, N x 2 n = ( )1/ 2 exp(− ) (1) 4πDt 4Dt where N is the number of electrons per unit area, D is the diffusion coefficient for high resisitivity silicon (39cm2/s), x is distance about the center of the distribution (cm) and t is time (sec). For a fully depleted pixel, the resultant cloud diameter at the frontside of the detector is only a function of sensor thickness and applied voltage.5 2kT x 2 DIA = [ THICK ]1/ 2 (2) q VSUB + VPIX where xTHICK is the sensor thickness, VPIX is the pixel photo diode bias, VSUB is the substrate voltage and kT/q is the thermal voltage (0.025V at 300K). The cloud diameter, DIA, is defined as ± 1σ where 68.2 % of the charge is contained in the cloud distribution (i.e., 2σ=2(2Dt)1/2). The corresponding transit time is, x 2 tr = THICK (3) u(VSUB + VPIX ) where µ is the silicon mobility (1500cm2/V-s). It is important to note that the diffusion cloud size increases proportionally to sensor thickness and decreases by the square-root of applied voltage (VSUB+VPIX). Figure 5 plots transit time and the resultant Gaussian 2σ charge cloud diameter as function of applied voltage for various fully depleted epi thicknesses (5, 10, 15, 20, 30, 40 and 50µm).