Fundamental Performance Differences Between CMOS and CCD Imagers

Fundamental performance differences between CMOS and CCD imagers: Part III James Janesick*a, Jeff Pintera, Robert Pottera, Tom Elliottb, James Andrewsc, John Towerc, John Chengd, Jeanne Bishopd

a Sarnoff Corporation, 4952 Warner Av., Suite 300, Huntington Beach, CA. 92649 b Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA. 91109 c Sarnoff Corporation, CN5300, 201 Washington Road, Princeton, NJ 08543-5300 dChronicle Technology, 4340 Von Karman Av., Suite 120, Newport Beach, CA. 92660

ABSTRACT

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Keywords: CMOS and CCD scientific imagers.

1. INTRODUCTION

This paper continues discussions on ‘fundamental performance differences of CMOS and CCD imagers’ stemming from three previous papers delivered on the subject1-3. The papers collectively demonstrate that significant progress has taken place for Scientific CMOS imagers in achieving equal to or better performance than the CCD. High performance implies very low read noise (1 e-), high quantum efficiency (transmission limited), deep depletion for near IR and soft x-ray charge collection efficiency (CCE) performance, low pixel cross-talk (high MTF), high charge transfer efficiency (CTE), 14-16 bit high dynamic range, high signal-to-noise for low contrast scenes and very high speed / low noise parallel readout using integrated designs. This paper is specifically focused on three main development areas; 1). Sandbox fabrication, 2). charge-coupled CMOS pixel development and 3). CMOS pixel MOSFET development. The last section of the paper is devoted to planned future developments of large high performing CMOS imagers for scientific applications.

2. SANDBOX FABRICATION

As successfully implemented in fabricating past high performance scientific CCDs, Sarnoff and its customers also rely on ‘Sandbox’ lot runs for CMOS imager development and prototyping purposes4. Multiple customers take part on these runs to share fabrication expenses and team in developing CMOS imager technology together (cost is proportional to the real estate occupied on the silicon wafer). Typically after an imager is developed with Sandbox, efforts for a specific customer are directed to a dedicated lot run in fabricating the production sensor. Sandbox lots are normally fabricated at Jazz Semiconductor using their 0.18µm CMOS process (although some fabrication work also takes place at other CMOS foundries). Sarnoff has also incorporated five custom implants to the base 0.18um process required for high performing CMOS pixels. Also, thick high resistivity epitaxial (epi) silicon and SOI wafers are often used for deep depletion near IR and x-ray imagers. Figure 1 shows an example Sandbox reticule layout currently under test. The design includes six small 496(V) x 512(H) Minimal Arrays,2 one large Minimal Array and a block of test ADCs that all occupy an area of

* e-mail: [email protected], Paper Number: 7439A-6, San Diego Aug 2009. approximately 22mm x 22mm. The 1536 x 1536 sensor is based on 8µm ‘five transistor pinned photo diode (5T PPD)’ pixels designed for a SNAP2 frame readout rate of 30 frames/sec. The small Minimal arrays contain 8µm, 16µm and 24µm 3TPPD and 5TPPD pixels and a wealth of development CMOS test pixels including a buried channel CMOSCCD. This particular Sandbox (Sandbox V) used 25 silicon wafers that were split for 3.3V and 5.0V processing. A 5V process allows high voltage operation for improved dynamic range, lower pixel cross-talk, deeper depletion and provides a thicker gate oxide compared to 3.3V processing (3x) to reduce poly gate leakage issues. Sandbox V incorporates many new CMOS features some that are discussed below. Test data from this Sandbox run will be shared in upcoming papers.

3. CMOS PIXEL DEVELOPMENT

3.1 Substrate Bias Sandbox V contains numerous experiments involving substrate bias aimed at maximizing CCE performance. Compared to CCDs, low pixel cross-talk is more difficult to achieve for CMOS especially for thick imagers that detect near IR and x-ray photons. For these sensors high resistivity epi silicon is an absolute requirement for deep depletion and good CCE. However, even when silicon is fully depleted, the desired low cross-talk may not be realized. Hence, an additional bias voltage across the imager called substrate bias is the only means to deal with the problem (other than just increasing pixel size). Following how very deep depletion CCDs handled the CCE problem,5 substrate bias can also significantly improve cross-talk performance for CMOS imagers. However, the technique is considerably more difficult to implement compared to CCDs, and therefore, is considered a ‘custom’ feature for any design attempted. Discussions below will only brief the reader on a few important aspects behind substrate bias inner workings leaving most technical details for another paper.

Figure 2 illustrates a cross-section of CMOS imager showing the substrate bias contact, pixels and drivers for the pixels. It is important to note that it is just not enough to simply deplete the entire structure with substrate bias. But in addition, a sufficient potential barrier must be realized between the pixel grounded p-wells and the bias to prevent (hole) leakage current flow. The required barrier height is primarily dependent on the positive bias potential applied on adjacent n+ regions (e.g., pixel photo diode) and the dimensions of the p-well and pixel photo diode. Figure 3a presents a PISCES (Poisson and Current Continuity Equation Solver) / SUPREM (Stanford University Process Modeling) simulation that plots potential through the pixel’s p-well region as a function of device depth. Photo diode bias is varied (0.4, 0.8, 1.2 and 1.6V). Note as the diode bias decreases the barrier height under the p-well also decreases signifying a limit to the amount of substrate bias that can be applied. To prevent leakage current from flowing, at least 500mV of barrier is usually required (i.e., 20kT). Figure 3b plots substrate current and bias showing where that limit occurs.

It should be mentioned that barrier height also decreases with silicon resistivity and increases with its thickness. Also, the width of the pixel p-well requires minimum design rules but not too small to cause pixel-to-pixel blooming. The photo diode should have the largest active fill factor possible for maximum substrate bias. As seen in Fig 2, digital logic elements contained on the imager (e.g., address encoders, pixel bipolar drivers, multiplexers, etc.) also rely on grounded p-wells for operation. It is not possible to ‘pinch off’ this circuitry from substrate bias as is done for the pixels. Instead a biased deep n-well implant is employed under these circuits to generate a sufficient barrier for substrate bias. The figure also shows that the substrate bias contact is far removed from the pixels. As it turns out, the pixel depletion region does not extend to the backside of the sensor if the depletion reaches the substrate contact first. The minimum separation dimension between the pixels and the substrate contact assumes that this distance is approximately equal to the thickness of the silicon. CCE improvements using substrate bias are discussed in the next section.

3.2 Pixel Cross-talk The other challenge for CMOS imagers to achieving good CCE performance is minimizing the transit time in moving signal charge to the target pixel’s collection region without significant diffusion among its neighbors. For example, Fig. 4a illustrates how a charge packet travels from the backside of the imager to the frontside by the electric field generated by the pixel and substrate bias. Figure 4b plots the potential versus depth as the substrate voltage changes from 0 to - 20V. The slope of these curves represents the field strength that increases with substrate bias. During transit, thermal diffusion takes place increasing the charge cloud size following a Gaussian distribution of,

N x 2 n = ( )1/ 2 exp(− ) (1) 4πDt 4Dt where N is the number of electrons per unit area, D is the diffusion coefficient for high resisitivity silicon (39cm2/s), x is distance about the center of the distribution (cm) and t is time (sec). For a fully depleted pixel, the resultant cloud diameter at the frontside of the detector is only a function of sensor thickness and applied voltage.5

2kT x 2 DIA = [ THICK ]1/ 2 (2) q VSUB + VPIX where xTHICK is the sensor thickness, VPIX is the pixel photo diode bias, VSUB is the substrate voltage and kT/q is the thermal voltage (0.025V at 300K). The cloud diameter, DIA, is defined as ± 1σ where 68.2 % of the charge is contained in the cloud distribution (i.e., 2σ=2(2Dt)1/2). The corresponding transit time is, x 2 tr = THICK (3) u(VSUB + VPIX ) where µ is the silicon mobility (1500cm2/V-s). It is important to note that the diffusion cloud size increases proportionally to sensor thickness and decreases by the square-root of applied voltage (VSUB+VPIX).

Figure 5 plots transit time and the resultant Gaussian 2σ charge cloud diameter as function of applied voltage for various fully depleted epi thicknesses (5, 10, 15, 20, 30, 40 and 50µm). Usually cross-talk becomes a serious performance issue when the cloud diameter grows to be comparable to the pixel size. For example, a 30µm thick sensor with VPIX=3.3V, VSUB=0V applied produces a 2σ cloud diameter of 7.5µm. For a 7.5µm pixel this diameter still leaves 32 % of the signal outside the target pixel. Figure 6 plots ‘point-spread’ responses from Eq. (1) for the same thicknesses as Fig. 5 with and without -20V substrate applied (VPIX=3.3V). Note without substrate bias applied (Fig. 6a), the 8σ ‘wings’ of the point- spread remain inside an 8µm pixel for tTHICK=10µm. With -20V substrate bias (Fig. 6b) the thickness can be increased to 20µm with full charge confinement. Also shown on the VSUB=0V plot is PISCES simulated point spread curve to cross check the equations above.

Fe-55 x-ray photons represent near perfect point source stimulus producing an initial 2σ cloud diameter of approximately 0.35µm.4 Figure 7 presents a Fe-55 x-ray image taken by a 15µm thick frontside illuminated CMOS Minimal Array with 8µm pixels. Figure 8 shows a corresponding simulated Monte Carlo response for the device with and without substrate bias applied. Note that the simulation plots assume DMAX=8σ diffusion circles to contain all charge. The solid and dotted circles represent cloud sizes for VSUB=0V and -20V respectively. Ideally the image and simulation should contain only x-ray events that only involve the target pixel, however because of diffusion, signal charge expands into neighboring pixels. Each x-ray event produces a different cloud size depending on where in the device the x-ray is absorbed. An x- ray absorbed at the immediate front surface creates a very small point-spread equal to the initial cloud generated by the x-ray photon. Those x-rays that interact near the epi-substrate interface exhibit the largest point-spreads (corresponding to DMAX labeled in the figure). For example, for 15µm epi DMAX=15.2µm for VSUB=0V and decreases to DMAX=5.2µm for VSUB=-20V. Figures 9 and 10 are similar results for 25µm epi silicon producing much greater charge diffusion clouds. For 25µm epi substrate bias is essential for an 8µm pixel imager to achieve good CCE performance.

It is important to point out that even with high resisitivity silicon and substrate bias that x-ray split events are still generated. To deal with split events we either discard them keeping only single pixel events or sum the pixels that make up a split event and suffer degraded energy resolution (because of the read noise increase). For example, Fig. 11 presents a single event x-ray histogram taken from a 15µm thick CMOS Minimal Array. Excellent energy resolution is achieved showing low level x-ray lines from the basalt target and Fe-55 source that would not be seen unless split events were discarded by a computer. For minimum charge splitting very thin sensors are required. For example, Fig. 12 presents simulated data for a fully depleted 5µm sensor built on SOI epi (refer to Fig. 16 discussions). With substrate bias applied, x-ray point-spread for most events is very close to the limit of the initial cloud diameter. Curiously, ultra thin

Figure 1. Sandbox V currently under test. Figure 2. Substrate bias for deep depletion CMOS imagers.

Figure 3a/b. Substrate barrier and related leakage current. Figure 4a/b. Cloud diffusion and transit time with substrate bias.

Figure 5a/5b. Transit time and diffusion cloud size with bias voltage. Figure 6a/6b. Point spread without and with substrate bias.

Figure 7. 15µm epi Fe-55x-ray split and single pixel events. Figure 8. 15µm epi Fe-55 x-ray substrate bias simulation.

Figure 9. 25µm epi Fe-55 x-ray single and split events. Figure 10. 25 µm epi Fe-55 x-ray substrate bias simulation.

Figure 11. Fe-55 and basalt single pixel x-ray histogram. Figure 12. 5µm SOI epi Fe-55 x-ray substrate bias simulation. (2µm) very small pixel (< 1.5µm) commercial BSI imagers are limited by this diameter. However, no single pixel events are observed since the initial 8σ cloud diameter is always greater than the pixel size.

The modulation transfer function (MTF) is routinely used to specify CCE performance.4 Diffusion MTF can be evaluated by taking the Fast Fourier Transform (FFT) of the point-spread responses shown in Fig. 6. Performing this operation produces the results shown in Figs. 13a and 13b. Note that spatial frequency is given in units of cycles/ pixel with Nyquist being at 0.5 cycles /pixel. Also shown is the pixel MTF response assuming a 100 % fill factor. For example, for VSUB=0V plot (Fig. 13a), the diffusion and pixel MTF are 0.33 and 0.63 respectively for 30µm thick epi silicon. The overall MTF is 0.20. The net MTF increases to 0.54 when a substrate bias of -20V is applied (Fig. 13b). There is one data point produced by PISCES to check MTF results (50µm silicon, VPIX=3.3V and VSUB=0V). PISCES can provide a sinusoidal stimulus at a desired optical wavelength to generate MTF directly. Agreement between equations and PISCES has been excellent.

MTF results in Fig. 13 again show the difficulty for thick CMOS imagers to achieve high CCE. The problem is compounded by the reduction of photo diode voltage as signal charge collects. This issue is particularly critical for the 5TPPD pixel which starts off with a potential that is approximately half the sense node voltage without charge (i.e., 1.5V for 3.3V processing). The PPD potential collapses with signal taking potential to near 0.5V degrading CCE significantly. Therefore, even a small amount of substrate bias is important for scientific CMOS imagers.

3.3 Silicon Point-spread analysis above assumes that the epi is fully depleted and produces a constant electric field throughout the layer. An imager fabricated with high resistivity epi can achieve this condition and potentially deplete to 50µm with 3.3V bias (refer to Fig. 14a). In contrast, commercial imagers that use 5-10 ohm-cm epi are far from achieving this depth even in absence of signal charge (<1-2µm is typical). Consequently MTF performance for commercial imagers is relatively poor for use in x-ray and near IR applications (unless field free material is removed and rear illuminated in exchange for significant QE loss). Figure 14b plots epi silicon resistivity as a function of depth for 15 and 25µm custom silicon typically used to fabricate Sandbox imagers. Note that the silicon exhibits a long epi ‘auto doped substrate tail’ characteristic of epi grown silicon. Full depletion for this silicon can only be achieved by removing some of the highly doped tail by thinning to the etch stops indicated (i.e., 13 and 23µm respectively). Figure 15a presents potential plots for 14µm epi showing potential, doping and electric field profiles as the substrate bias is varied. For this silicon the etch stop required for full depletion and constant electric field is approximately 12µm.

Sandbox V imagers are also fabricated on ‘silicon on insulator (SOI)’ epi silicon (refer to Fig. 16a). SOI is advantageous over conventional silicon because the ‘box’ oxide layer shown acts as the perfect etch stop that makes thinning easy and precise. Also SOI does not have the troublesome auto doped tail mentioned above. Instead high resistivity silicon can be maintained throughout the epi to ‘box’ oxide layer. Lastly, very thin imagers can be fabricated using SOI because the epi layer grown can be as thin as desired (refer to Fig. 12 and 16 b). Two types of SOI are shown in Fig. 16a. The first is referred to as ‘non accumulated’ SOI with >10,000 ohm-cm high resistivity epi to the oxide layer. For this epi, both the substrate and the oxide layer are removed and accumulated using standard backside illumination passivation techniques.4 The second type of SOI is called ‘self accumulated’ manufactured by a propriety process developed at Sarnoff.6 For visible imaging applications the substrate is simply thinned to the oxide layer. No further backside processing is necessary unless the remaining oxide needs to be removed for UV and soft x-ray applications. Figure 16b plots theoretical quantum efficiency with wavelength for a variety of membrane thicknesses (without anti reflection coatings applied). Note that the UV QE is not dependent on thickness as visible and near IR wavelengths are. This characteristic is attractive for semi ‘IR blind’ imagers. Ultra thin detectors (2µm) are also required by commercial backside illuminated imagers with very small pixels because of ‘optical cross talk’ for low f-number camera systems.

3.4 Read Noise and Extended Dynamic Range Read noise is also dependent on depletion depth especially for 3TPPD pixels. As discussed in previous papers, low noise requires very high conversion gain (V/e-) or low sense node capacitance. Coincidently for CMOS pixels approximately 2-3 fF of sense capacitance is necessary to achieve 2-3 noise electrons. The net capacitance for a 3TPPD pixel is associated with the diode’s n+ sense contact, MOSFET source follower gate, and diode to p-well side wall /vertical capacitances. Figure 17 plots just the diode capacitance as a function of bias voltage for 8µm and 24µm square PPDs without a n+ sense node contact. The analysis assumes >10,000 ohm-cm epi silicon and a 2µm grounded p-well used to isolate neighboring pixels. As bias is applied the diode begins to deplete which reduces side wall and vertical capacitances. Eventually the n part of the diode completely depletes leaving mainly vertical capacitance. The net capacitances when fully biased are 0.8fF and 0.5 fF for the 24 and 8µm diodes respectively. The third dotted curve shown assumes an n+ contact placed in the 8µm diode producing a mixture of vertical and n+ to p-well side wall capacitance of 1.2 fF. Note that the 24µm pixel will have lower capacitance because it isolates the n+ region from the p- well better than the 8µm pixel. Experiments to verify Fig. 17 results are on Sandbox V.

As the sense node conversion gain (V/e-) is increased to achieve low noise performance the charge capacity decreases. To extend the useful dynamic range for larger signals Sandbox V includes an additional pixel transistor on some of its 3TPPD and 5TPPD imagers that allows the user to decrease V/e- on command. As illustrated in Fig. 18a, this is accomplished by switching a metal-insulator-metal (MIM) capacitor onto the sense node with a small MOSFET. Fig. 18b, plots the conversion gain as a function of total capacitance related to the sense node. The gain can be changed very rapidly. For example, for a 3TPPD pixel a row of pixels can be read twice with low and high V/e- for extended dynamic. It is also possible to use the 5th transistor of a 5TPPD to extend the dynamic range using the reset timing technique described in Ref. 7 on XDR technology.

3.5 5TPPD Charge Transfer Efficiency Figure 19a presents a 5TPPD pixel edge response to a LED light source that is turned on and off. Ideally a perfect square-wave should be observed for good CTE without deferred charge on the falling edge of the response. However, careful examination of the data shows that the CTE problem exists. For example, Fig. 19b presents a magnified view (10x) showing deferred charge more clearly. Reducing the light level produces less deferred charge in terms of proportional loss. This characteristic is opposite to CCD behavior where CTE usually degrades with decreasing signal level.4 Figure 20a demonstrates excellent CTE performance when the light is lowered to a 1 e- p-p level. Figure 20b plots CTE as a function of signal level showing that performance approaches unity as the signal level approaches zero. CTE behavior is related to the sense node potential as discussed in Sec. 3.6.

Line stacking and histogram Fe-55 x-ray responses generated by a 5TPPD Minimal Array are shown in Fig. 21. Results confirm that ideal absolute CTE performance is being achieved at 1620 e-. Digital CDS (dCDS) signal processing and progressive scan readout is employed to generate the plots. Readout starts by resetting the first row of pixels followed by sampling reference levels and storing values in a computer. Next the transfer gate is activated to transfer charge from the PPD to the sense node. Video samples are then taken and stored. Figure 22a shows the reset and video levels before this subtraction is performed. The computer then differences the reset and video samples to remove reset and offset fixed pattern noise to produce the resultant x-ray responses shown. Analog CDS (aCDS) signal processing can also be employed in generating the x-ray response by using the on-chip aCDS provided on the Minimal Array.2 This circuitry consists of 512 clamp switches, clamp capacitors and buffer source followers to perform the aCDS operation. Readout for this mode of operation starts by also resetting a row of pixels. The clamp clock is also turned on at this time and released slightly before the transfer gate clock is activated to transfer charge. Reset and offset noise are taken out at this point. After the transfer gate is clocked some settling time is required before an off-chip ADC scans, encodes and sends the final video levels to a computer. The row readout process is repeated for both dCDS and aCDS progressively until a full frame is in a computer. It should be mentioned that aCDS and dCDS processors achieve approximately the same read noise floor although dCDS is always higher (refer to Sec. 3.11).

Figure 22b shows how Fe-55 x-ray events are affected by the transfer gate clock voltage as labeled. When the clock amplitude is not adequate deferred charge (or image lag) is seen. For this imager complete charge transfer takes place when TG>2.4V. Although CTE performance is excellent, CCE is very poor for this experimental sensor. Figure 23 compares the number of split and partial x-ray events with line stacking and histogram plots. This particular imager was fabricated on 3 ohm-cm / 7µm epi silicon which produces a depletion depth of less than 1µm. Hence, most of the epi thickness is undepleted leading to mostly split events. Also, read noise is higher for the imager compared to sensors built on 10,000 ohm-cm epi (7 e- compared to 3 e- for the same pixel design and PPD implants).

3.6 5TPPD Charge Transfer Time and Nonuniformity Transferring charge from the PPD to sense node should take place very rapidly, ideally approximately 10 ns depending on charge packet and pixel sizes. However, in practice theoretical speed is rarely observed because charge is held back

Figure 13a/b. MTF versus epi thickness and substrate bias. Figure 14a/b. Depletion depth vs epi resistivity and Sandbox V silicon.

Figure 15a/b. Potential and electric fields with substrate bias. Figure 16a/b. SOI epi and QE responses with thickness.

Figure 17a/b. Diode capacitance versus voltage and 3D simulation. Figure 18a/b. Pixel gain V/e- switch for extended dynamic range. by transfer gate potential ‘barriers’ and/or ‘pockets’ created by improper PPD implant dose/energy and placement in the region.4 For low light levels charge rapidly moves under the transfer gate because fringing electric fields between the PPD and sense node regions are greatest. CTE performance under these transfer conditions is usually excellent. As the signal level increases the fringing field strength and related transit time between the regions decreases. Also transfer gate barriers and pockets become more pronounced for trapping along with more opportunity for charge to become trapped within transfer gate surface states. At the full well fringing fields become nearly nonexistent which results in the maximum trapping condition. Figure 24 shows a 5TPPD pixel with severe pocket and barrier trap issues that would result in very poor CTE at any signal level. Charge can only slowly escape traps by thermal diffusion. To quantify the speed penalty related to traps, Fig. 25a presents a potential diagram showing three different barrier heights at the leading edge of the transfer gate. The magnified view in Fig. 25b labels the barrier height and the required time to transfer charge in each case. For example, a barrier height of 100mV (4kT) requires 100 ns to thermally transfer charge from the PPD to the sense node region, approximately 10 times longer than ideal.

High speed CTE measurements are impacted by the barrier problem discussed above. For example, Fig. 26 shows a square-wave LED response generated by a single 5TPPD pixel taken at four different transfer gate ‘on’ times (50, 100, 150 and 200 ns). Note that the response improves as the clock width increases until at 200 ns respectable CTE performance is achieved. Figure 27 presents a row of 475 5TPPD pixels showing that each pixel exhibits a different response time. For this test a pixel is addressed, LED flashed or not flashed, charge transferred and measured. The sequence is repeated for every pixel in a row. A high-light level is used in generating the top trace using a clock width of 50ns whereas the middle trace lowers the light by ten times to show ‘CTE nonuniformity’ more clearly. The bottom trace is generated with a clock width of 400 ns which significantly improves CTE performance. However, a small number of very slow pixels are still present even at this wide clock width.

Assuming that a transfer gate barrier (or pocket) does not exist, charge transfer time is ultimately limited by thermal diffusion. This limit applies primarily to large pixels where transfer gate fringing fields don’t extend across the entire PPD region to aid in the charge transfer process. To increase speed performance the ‘ring’ pixel shown in Fig. 28 was invented. For this architecture the sense node region is not on the side of pixel with the read MOSFETS but instead located dead center of the pixel. Hence, charge is transferred from all directions into the sense node reducing charge transfer time. In addition, to generate fringing fields at the very edges of the PPD region an implant is employed that ‘steps’ the potential in the direction of the sense node as illustrated to further decrease transfer time. The pixel can potentially deliver high speed performance for 5TPPD pixels up to 24µm. Also ring architecture is more adaptable to substrate bias. Test results for the pixel will be forthcoming on Sandbox V.

3.7 5TPPD Transfer Noise When the transfer gate for a 5TPPD pixel is driven hard such that its potential reaches that of the sense node, read noise typically increases slightly. For example, Fig 29 plots read noise as a function of clock voltage for a 5TPPD test array. The noise increase is likely related to charge sloshing back and forth between the PPD and sense node as a result of charge trapping under the transfer gate. To avoid the problem there must be a wide enough transfer gate clock window for both good CTE and low noise. For good CTE a transfer gate voltage of at least 2.5V is required whereas the onset of noise increase takes place at 3.5V. Hence, a 1V clock window is available for operation for the pixel in Fig. 29. The noise problem can be reduced by placing a boron implant at the leading edge of the transfer gate as illustrated Fig. 30. The implant provides a barrier step to prevent charge from moving back to the PPD whenever the transfer gate is over driven. Trapped charge will remain in the sense node region allowing elevated clock drive. Figure 29 also plots read noise for a 5TPPD fabricated with this implant in place showing the noise improvement. The read noise does not increase when the transfer gate potential becomes greater than the sense node. It is also important to point out that the transfer gate barrier implant prevents most thermal dark current generated under the transfer gate from reaching the PPD region. Although this technique is valuable for progressive scan readout imagers, SNAP readout will still have transfer gate dark current since charge is stored on the sense node. However, transfer gate dark current is always less than sense node dark current (refer to Sec. 3.9).

3.8 5TPPD Charge Capacity Adjusting the PPD implants and working potentials to achieve optimum charge capacity has been discussed previously.2,3 Variables such as source follower saturation and sense node gain (V/e-) are important contributing factors in setting the PPD potential properly. However, it should be noted that elevating the PPD potential to increase PPD

Figure 19a/b. Square-wave CTE responses showing deferred charge. Figure 20a/b. One electron response and CTE with signal.

Figure 21a/b. 5TPPD Fe-55 x-ray responses. Figure 22 a/b. dCDS samples and CTE versus TG clock voltage.

Figure 23a/b. Comparison of single and split Fe-55 events. Figure 24.Transfer gate CTE barrier and pocket traps. charge capacity also reduces the field strength between the sense node and PPD region reducing CTE performance as discussed previously (Sec. 3.6). For our pixels, optimum CTE and full well performance is achieved by adjusting the PPD full well slightly greater than source follower saturation. For example, Fig. 31 shows a set of photon transfer curves that experimentally finds the optimum PPD implant dose for this condition. Optimum full well occurs at a charge level of 21,000 e-. The two other curves shown are limited by PPD full well with implant doses of 9 % and 18 % less than the optimum.

For optimum charge capacity the transfer gate is clocked slightly negative in the off state. This clocking strategy only applies to a simple native epi transfer gate without additional barrier implantation. The negative bias produces an effective barrier between the sense node and PPD regions. For example, Fig. 32a presents a potential diagram showing that TG=0V does not present a complete barrier to signal due to fringing fields. Hence, charge can thermally escape the PPD region to the sense node reducing full well. The problem becomes much more pronounced when the transfer gate length is less than 1µm. Figure 32b shows surface potentials in reaction to the negative bias. As the bias is applied the surface goes into accumulation as a result of holes populating the surface supplied by a neighboring p-well region. The accumulated state pins the surface and produces a high field condition across the oxide leading to a familiar CCD problem called ‘excess charge’.4 Figure 33a plots dark current for a row of 5TPPD pixels with three different transfer gate bias conditions. When –TG=0V that TG/PPD dark current is 27 pA/cm2 and increases rapidly as the -TG voltage is moved more negative increasing excess charge generation. The transfer gate leakage problem can be curtailed with 5V CMOS processing which provides a thicker oxide.

3.9 5TPPD Sense Node Dark Current One of the most critical performance differences between CCD and CMOS imagers is related to sense node contact dark current generation. For CCD readout, charge only spends a very short time on the sense node for readout, at most a few micro seconds. In contrast for charge transfer CMOS SNAP imagers, the sense node must act as a storage site to hold charge over the course of a frame time. Previous papers demonstrated that the sense node generates enormous amount of thermal dark current compared to other pixel dark current sources.2,3 For example, the dark current generation rate for the PPD region is typically below 10 pA/cm2 @300K whereas the sense node can generate up to 1,000 times more than this. Therefore, dark shot noise generated on the sense node is often much greater than the source follower noise even at 30 frames/sec. For example, Fig. 33b plots dark current rate (e-/sec) versus operating temperature showing that room temperature (27 C) generates 40,000 e-/sec assuming 10 nA/cm2 or 1333 e- per frame time and a dark shot noise of 36 e- . To achieve lower read noise, cooling the detector is required (from Fig. 33b approximately -43 C will drive the dark shot noise down to 1 e-). On the other hand, reading the same detector progressively (or rolling shutter) does not require cooling resulting in dark current generated by the transfer gate and the PPD regions. In this case dark current can be limited to approximately 10 pA/cm2 producing 1.3 e- per frame time or roughly 1 e- of shot noise.

Figure 34a shows that sense node dark current and bias voltage (VREF) increase together implying that dark current rate is nonlinear with signal collected. Figure 34b plots the nonlinearity (relative to mid scale) as a function of integration time for 256 pixels with VREF=3.3V. This undesired characteristic makes it difficult to remove dark current fixed pattern noise through subtraction. It should be mentioned that 3T CMOS pixels are also limited by sense node contact dark current since a metal contact is made to the photo diode. Hence, sense node dark current is a fundamental problem for all CMOS pixels whereas the CCD is not. Development work on reducing sense node dark current has focused on custom contact etches, low energy contact implants and annealing cycles. Unfortunately, results have been a hit and miss game producing inconsistent performance from lot run to lot run. The lowest sense node dark current achieved using our processes is 0.1 nA/cm2 referred to an 8µm pixel area. In reality dark current generation per cm2 of active area is much higher for the sense node. The sense node area here is 0.25µm2 which translates the dark current rate to 250 nA/cm2. Dark current and QE performance are usually specified on the entire pixel area at 300K.

3.10 Image Signal-to-Noise The Minimal Array does not usually contain a full array of identical pixels. Instead, dozens (sometimes hundreds) of different experimental test pixels are integrated on the array for development and optimization purposes. Therefore, generating a conventional full frame image for these arrays is not possible. However, an ‘EPROM imaging’ technique described here can be employed to give the reader some feeling for full framing capability for arrays like this. Figure 35 shows the set up used to do this which is composed of an EPROM, digital to analog converter (DAC), voltage to current converter and LED light source that will stimulate the imager. To use the system we start by first finding a test target that

Figure 25 a/b. TG CTE barrier and associated transfer times. Figure 26 a/b. Square-wave CTE with TG clock width.

Figure 27. Pixel to pixel CTE nonuniformity with TG clock width. Figure 28. The ‘ring’ pixel for high speed / large 5TPPD pixels.

Figure 29. CTE read noise with TG clock voltage. Figure 30. Transfer gate implant for improved performance. will become a full image generated by a single test pixel, row or multiple rows of pixels (typically found on the Web in JPEG, TIF, etc. format). Next the pixel grey level values from the target are stored into the EPROM (via EPROM programmer). The word width for the EPROM can be adjusted according to the desired dynamic range of the image found, e.g. 8-bits for 255 grey levels, 12-bits for 4096, etc. The output of the EPROM is connected to a digital-to-analog converter (DAC) which converts each binary number of the EPROM to a voltage. The DAC output voltage is then converted to a current (e.g., common source transistor) which drives the LED. Next the x-y pixel addresses provided progressively drive both the EPROM and Minimal Array to keep them fully synchronous. As this is done, the LED is flashed in concert pixel by pixel in producing a full image. Note, if only a row of test pixels is available, the y address to the imager is fixed to that row whereas the EPROM cycles through all y addresses. To image with a single pixel, both x and y addresses to the imager are fixed to that pixel. Note that the pixel output voltage from the imager is proportional to the original pixel gray scale level in the target image.

The test target shown in Fig. 36a was loaded into EPROM image generator to produce a full image using a single row of 5TPPD pixels contained on a Minimal Array. The light intensity of the LED used to stimulate the imager was set to yield an average signal level of 70 e-/pixel. The noise contained in the image is composed of read noise, photon shot noise and pixel-to-pixel fixed pattern noise. The signal-to-noise (S/N) of the image can be calculated through the relation,7

S M S = I I (4) 2 2 1/ 2 N (σREAD + SI + (PNSI ) ) where SI is the average signal of the image (e-), σREAD is the read noise (rms e-) and PN is the pixel-to-pixel fixed pattern noise factor (FPN). The constant MI is defined as the ‘image modulation constant’ given by,

δI M I = (5) SI where δI is the amount of modulation (or contrast) of the image (rms e-). Figure 36b plots S/N performance across the image for two different read noise levels produced by the imager (2 and 9 e- rms). For the 2e- case the S/N varies from 4.5 to near zero as the contrast decreases.

Figure 37 and 38 shows a second test target and resultant EPROM image taken from a different row of 5TPPD test pixels with lower read noise. There are five outlined regions that make up the composite image with increasing exposure (labeled 1 thru 5). The average signal level (SI) increases from left to right from 2.7 to 83.9 e- with a corresponding contrast signal of 1.59 to 65 e- rms (δI). Figure 39a presents the signal histograms for regions 1 and 5. The image demonstrates remarkable 5TPPD S/N performance. Such imaging is only possible because of low read noise (1.6 e- rms) and perfect CTE using progressive scan operation. The resultant S/N performance is also indicated, using Eq. 4, which varies from 0.70 to 7.1. Pixel FPN has been removed from the image, by flat fielding, although at these signal levels very little FPN is observed (typically FPN=1 % for CMOS and CCD imagers). For the most part, photon shot noise dominates S/N performance for regions 3-5 regions because read noise is so low.

It should be pointed out that the image modulation constant, MI, varies slightly (0.59 to 0.78) indicating the contrast between the regions is similar. The modulation on the left side of the image is slightly less because the automobiles in the parking lots produce less shadowing and contrast than the buildings do on the right side. It is interesting to compare the ideal target image in Fig. 37 to the EPROM image as S/N degrades where automobile details nearly vanish to photon shot and read noise. It is also interesting to note when comparing low noise CMOS and CCD imagers with the same read noise floor, that CMOS images appear to be somewhat ‘spiky’ even though contrast features appear more pronounced. The perceptible difference is because CMOS read noise is limited by ‘random telegraph signal (RTS)’ noise1 whereas CCD noise is limited by flicker (1/f) noise (refer to Sec. 4.1 below). Figure 39b demonstrates how RTS noise for six noisy pixels change with time for 100 columns showing half dozen high noisy RTS pixels. Figure 40a presents an oscilloscope trace taken directly at the source follower output for a noisy pixel showing strong RTS modulation. Figure 40b presents a ‘dark frame’ histogram generated by the imager in Fig. 38. The average read noise is 1.6 e-, however,

Figure 31. Photon transfer full well with different PPD implants. Figure 32 a/b. TG barrier full well problem and accumulation.

Figure 33a/b. TG dark current with clock voltage. Figure 34a/b. Sense node dark current and related nonlinearity.

Figure 35. Lens-less EPROM image generator. Figure 36 a/b. EPROM test target image with measured S/N performance.

Figures 37 and 38. Test target and EPROM image taken with 512 5TPPD pixels noise characteristics do not follow a Gaussian distribution but exhibits a ‘RTS skirt’ which is responsible for the ‘spiky’ appearance of the image.

3.11 Digital CDS versus Analog CDS Deciding between dCDS or aCDS processing depends on the CMOS readout mode employed. For example, dCDS is necessary to read 3T CMOS pixels to achieve very low noise. 5T CMOS pixels that read progressively (or rolling shutter) typically use an aCDS processor whereas SNAP readout requires dCDS for low noise. Both processors perform the same function by taking two samples before and after charge has been collected. The difference between the samples produces the desired video signal without kTC reset or offset fixed pattern noise. For aCDS this subtraction is performed by analog circuitry (usually by a clamp switch, sample and hold and two storage capacitors) while for dCDS the samples are directly sent to a computer and differenced there. An aCDS signal chain delivers the lowest read noise possible because the sample-to-sample time and bandwidth are optimally selected by the user. In contrast, dCDS processing does not deliver ideal noise performance because the sample-to-sample time is forced by the frame and integration times required (which can amount to hours for some applications). However, the bandwidth for the two processors is usually same.

Figure 41a plots aCDS and dCDS sinusoidal frequency output responses in reaction to RTS noise (refer to Eq. 7 for RTS noise characteristics). A sample-to-sample of ts=1µs and a dominant time constant of τD=0.5µs (equivalent to a bandwidth of 1/4τD) represents timing conditions for the aCDS processor. The relation ts=2τD is considered optimum 4 timing for lowest noise performance and is assumed in the figure. Sample-to-sample times greater or less than 2τD produce higher noise floors in terms of rms e-. The other curve shown with ts=2µs is not optimum and represents dCDS processing. Figure 41b uses ts=1µs (aCDS) and 10µs (dCDS) showing how the frequency response for dCDS processing changes as the sample-to-sample time increases.

The areas under the curves shown in Fig. 41 are proportional to the read noise floor. Figure 42a plots the ratio of the areas as the sample-to-sample time is varied. Note that the noise increases with ts > 1us and τRTS. These results are expected since longer sample times beyond 1µs do not efficiently reject lower frequencies. Note for white noise also shown in the plot that the area ratio is unity and independent of sample-to-sample time. For flicker 1/f noise the ratio increases to a value of 21/2 with sample time. Figure 42b shows experimental 5TPPD data generated by aCDS and dCDS processors with ts=3µs (aCDS) and ts=10ms (dCDS) respectively with τD=1.5 µs. The average noise floor of the aCDS processor is 3.07 e- whereas the dCDS processor produces 4.47 e-. It is interesting that the noise ratio is approximately 21/2 implying that the ‘average’ spectral noise of the pixels is flicker the same as CCD (refer to Eq. 6).

For CMOS aCDS processing, column clamp and sample and hold circuits are usually available on-chip to deliver very high speed operation while achieving low noise. Note if only a clamp circuit is provided (used in conjunction with an off-chip ADC with sample and hold), that sample-to-sample time increases as the columns are scanned resulting in a read noise that increases with column count. The clamp and sample and hold circuits require large storage capacitors to keep kTC noise less than pixel source follower noise (i.e., less than 1 e- rms). Figure 43 plots kTC noise referred to the sense node as a function of capacitance for varying µV/e-. For example, assuming 40µV/e- conversion gain, a capacitance of 4pF generates 1 e- of kTC noise. This is a sizeable on-chip capacitor given that stacked MIM capacitors only offer 4fF/µm2. Capacitance can be reduced if a low noise pre-amp is employed in each column (the cap size reduction is proportional to the pre-amp gain).

3.12 CMOSCCD and Photo-gate Pixels CCDs have been fabricated using the custom implants offered by Sandbox processing. For example, Fig. 44a shows a surface channel 4-phase, 8µm pixel, 512(H) x 128(V) CMOSCCD aimed at ‘time delayed integration (TDI)’ imaging applications. Note that CMOSCCD technology does not have a horizontal register compared to conventional CCDs. Instead the columns of the imager are addressed and read out in parallel using 512 aCDS column circuits similar to how a row of 5TPPD CMOS pixels are read. Therefore compared to conventional CCDs, high speed horizontal clocking and related CTE issues don’t exist for CMOSCCDs. CMOSCCD also provides the low power bipolar on-chip drivers for the four CCD vertical phases. Dynamic range can also be extended by using the selectable MIM cap circuit discussed in Fig. 18. It is also possible to incorporate both a TDI CMOSCCD with a framing CMOS imager on the same chip.

Figure 39a/b. Image histograms for Fig. 38 and RTS noise image. Figure 40a/b. RTS scope trace and noise histogram for Fig. 38.

Figure 41a/b. CDS frequency response to RTS noise. Figure 42a/b. CDS noise ratio and test aCDS/dCDS noise data.

Figure 43. kTC noise produced by sample and clamp capacitors. Figure 44 a/b. CMOSCCD and CTE response to 3 illuminated slits. Figure 44b presents CTE measurements generated by the CMOSCCD imager in Fig. 44a in response to three illuminated slits. The four phases of the device are clocked from 0V to 2V. Charge is transferred from right to left in the figure. As expected, deferred charge CTE tails caused by surface state trapping are observed. To avoid surface state trapping, Sandbox V (Fig. 1) focuses on buried channel CCD and photo-gate CMOS pixels. For example, Fig. 45a shows simulated buried channel potential wells for a CCD at different gate voltages. In general, CCDs achieve optimum charge capacity when surface and bloomed full well take place together.4 This condition occurs for the simulation at a gate voltage of approximately 2.0V with a surface to max potential barrier of 1.6V as indicated. Figure 45b is a corresponding plot of potential versus gate voltage for three different normalized buried channel implant energies (En=1, 0.75 and 0.5). Note that clocks can be taken into the inversion region with a gate voltage of -1V to reduce dark current and eliminate surface residual image.4 However, excess charge (gate leakage) through the thin oxide may prevent this mode of operation depending on integration and frame readout times. Fortunately, residual image can be removed by briefly (micro-sec) taking the imager into inversion before an exposure is taken.

Sandbox V CMOSCCD and buried channel PG pixels are primarily based on the 5V, 0.18µm CMOS process for optimum CTE, CCE, low gate oxide leakage and full well performance. One of a few drawbacks of 3.3V processing is the buried channel can not run entirely to the sense node. Instead for charge capacity reasons, the channel must end at the leading edge of the ‘last gate’ of the vertical CMOSCCD register (or the leading edge of the transfer gate for the photogate pixel). However, the buried channel is not self aligning (as PPD implants are) making placement of this edge uncertain and very critical on CTE performance. For example, Fig. 46a shows potential diagrams for a PG pixel where each of the four curves presented represents a different implant recipe in terms of energy and dose. Note that two of the implants produce a barrier, one implant produces pocket and the forth produces an ideal potential profile for good charge transfer. The potentials and traps change significantly with implant position (pockets turn into barriers and vica versa). The 5V process permits the buried channel to extend to the sense node to avoid alignment and trap issues.

Unlike CCD fabrication where multiple levels of poly silicon are used for the gates, only a single level of poly is typically offered by CMOS foundries. This restriction forces pixel designers to place a small gap between phases (< 0.25µm). The gaps can potentially degrade CTE performance especially near full well conditions where fringing fields between phases are essentially non existent. For example, Fig. 46b plots the maximum potential across three phases for two different buried channel implant energies. The gates are all held at 0V for worst case trapping conditions. The high energy implant produces a deep channel with a trap depth of 0.04V whereas the low energy implant produces a shallow channel of 0.17V depth. Consequently, CMOSCCDs typically use a high energy buried channel implant for maximum fringing fields.

3.13 Radiation Damage Radiation damage tests on CMOS imagers expand on previous tests performed.2,3 In general, 3TPPD and 5TPPD imagers can handle Co-60 gamma-ray doses up to 2Mrd without too much difficulty. For example, source follower read noise and CTE are only slightly affected by dose levels this high. Figure 47 shows Fe-55 x-ray responses generated by a 3TPPD pixel exposed up to 1Mrd. The K-α and K-β lines are well separated signifying that read noise and CTE performance hold up to the dose (5TPPD CMOS pixels exhibit similar responses). The 1Mrd response shows a slight energy resolution reduction but this problem is attributed to a thermal dark current shot noise increase. Figure 48 shows 3TPPD photon transfer responses taken at a 1Mrd dose level. Again very little change in the responses takes place indicating that flat-band shift associated with the 3T read MOSFETs is negligible (< 0.5V). Strictly for entertainment purposes, Fig. 49 shows a 2k x 2k, 2Mrd 3TPPD ERAM image of Niagara Falls during the winter time. Figure 50 is a magnified view of the image pointing out two automobiles traveling on the highway. Other than requiring a considerable amount of cooling to take the image (-90 C), the pixels operate fairly normally as though they had not been exposed to radiation.

Despite the fact that read noise, CTE and flat-band shift characteristics are significantly more tolerant to radiation sources than the CCD, CMOS still exhibits a significant Achilles heel. That is thermal dark current in reaction to high energy radiation sources. Of all dark sources within the pixel, high dark current generated by the sense node contact is fundamentally the most concerning because there is no apparent solution to minimize the problem (short of cooling the device). The 3T and 5T pixels are both vulnerable to the dilemma although the 5T when read progressively for the most part circumvents the issue (similar to how CCDs read images where sense node dark current is never a factor). However, even with progressive readout the PPD region can be highly sensitive to radiation damage.2,3 Fortunately, it has been

Figure 45a/b. BC CMOSCCD potentials and transfer curves. Figure 46a/b. Trap issues for BC CMOSCCD and PG pixels.

Figure 47. Fe-55 x-ray responses at various radiation dose levels. Figure 48. Photon transfer plots for baseline and 1 Mrad dose.

Figure 49. 2 Mrad (Co-60) 2k x 2k EPROM image of Niagara Falls. Figure 50. Magnified view of Fig. 49 showing two cars. demonstrated that PPD dark current can be controlled by using a higher pinning implant dose to assure that surface remains pins and dark current generation stays in check.

4. CMOS PIXEL MOSFET DEVELOPMENT

4.1 Random Telegraph Signal and Flicker Noise Figure 51 presents raw noise traces taken from different sized 3TPPD pixel source follower amplifiers. Note that the smallest amplifier has a ‘spiky’ appearance generated by RTS whereas the largest amp is more uniform. As the geometry increases, RTS noise changes into flicker (1/f) noise because the number electron traps under MOSFET gate increase and their modulation strength become less significant on the drain current.1 Figure 52 presents noise histograms for small and large amplifiers. Data is fitted to a normal curve from the average noise measured (104 and 58 DN rms respectively). The large amp is Gaussian distributed indicative of flicker noise whereas the small amp exhibits an ‘RTS noise skirt.’ This signifies that some pixels are RTS noise limited whereas other pixels are flicker and white noise background limited.

CCD amplifier noise has been described by the relation,4

f S (f ) = W 2 (1+ ( c )m ) (6) DET f

1/2 where SDET(f) is the detectors noise power spectrum, W is the source follower thermal white noise (V/Hz ), fc is the flicker noise corner frequency and m is the slope of the 1/f noise. The constant ‘m’ has been somewhat of a mystery that varies for small CCD amplifiers. The deviation can be explained by recognizing that RTS noise varies with a 1/f2 slope with a corresponding noise power spectrum of,1

2(R ∆I)2 τ L RTS (7) SRTS (f ) = 2 4 + (2πfτRTS ) where ∆I is the MOSFET drain current modulation (rms A), RL is source follower load resistance (ohms), τRTS is capture/emission RTS time constant and f is frequency (Hz). Therefore, for pixel amps with a mixture of RTS and background 1/f noise we should expect the overall noise spectrum to vary with a slope between 1 and 2 in which the constant ‘m’ represents.

Figure 53a presents noise histograms generated by 3800 source follower amplifiers showing both small and large geometries. The small amps exhibit a read noise range of 35-300 DN rms by RTS while the large amp noise varies from 40 to 90 DN rms with flicker noise. Figure 53b is the same data expressed in noise electrons. The small amp again shows a wide noise distribution, however, the average read noise is much lower because the large amps have lower V/e- conversion gains. Figure 54a plots read noise as a function of MOSFET gate width for the two channel lengths in DN and electron units. As expected, noise decreases linearly with MOSFET gate width. When plotted in electron units as in Fig. 54b, noise increases linearity with gate width. Figure 55a plots the conversion gain (V/e-) as a function of gate width separating source follower MOSFET capacitance and diode capacitance. Note that the conversion gain can be more than 100µV/e- when the diode capacitance is negligible (which can be the case for 3TPPD and 5TPPD pixels). Figure 55b plots capacitance (fF) versus gate width for both cases. Sub fF capacitance is achieved for sub micron gate widths for the 0.64µm gate length MOSFET.

4.2 Buried Channel MOSFETs Besides the PPD which naturally operates as a buried channel structure for 5TPPD pixels, CMOS designers are also applying buried channel to other pixel features. For example, photogate pixels and CMOSCCDs can benefit enormously from buried channel technology to achieve high CTE performance without surface trapping. Also buried channel MOSFETs, the subject of this section, reduces RTS noise and increases the dynamic range by reducing MOSFET threshold voltage.8 Figure 56a plots potential as a function of depth for a family of gate voltages for a standard surface channel MOSFET. Note that MOSFET drain current flows at the surface because the maximum potential is located there. The surface is also where carriers can become trapped in Si-SiO2 interface states leading to RTS noise. In

Figure 51. Raw source follower noise responses with SF geometry. Figure 52a/b.RTS and flicker noise histograms with geometry.

Figure 53a/b. Pixel amplifier noise histograms with amp geometry. Figure 54a/b. Read noise (DN and e-) versus gate width.

Figure 55a/b. Sense node V/e- and capacitance versus gate width. Figure 56a/b. Surface and buried channel MOSFETs. contrast, Figure 56b presents a cross-section of a buried channel MOSFET that employs a shallow arsenic implant. The equal potential contours show that the maximum potential shifts approximately 0.02µm below the surface forcing drain current to flow in the bulk. In doing so, RTS noise decreases since less drain current interacts at the surface. Also, the modulation strength of traps at the surface is less influential on bulk carriers. The Coulomb force around a trap extends approximately 0.02µm, coincidently the same depth as the buried channel.9

Figure 57a plots the current density (A/cm2) versus depth for a buried channel MOSFET. Note that drain current flows in the bulk at a low gate voltage (or high signal level). However, for a high gate voltage (or low signal level) the drain current begins to interact with the surface. This condition is not desirable because low signal measurements require low RTS noise. Figure 57b plots channel potential with depth showing that a gate voltage of 1.0V produces a thermal barrier of 500mV which will prevent carriers from interacting with the surface. Increasing the gate bias to 3V lowers the barrier to 200mV somewhat marginal for surface isolation (at least 10kT is required for a good surface barrier). Therefore, for optimum buried channel operation it is important that the gate bias be adjusted carefully until there is a sufficient surface barrier for low RTS noise while maintaining high dynamic range. Sandbox V tests will verify this condition.

Figure 58a presents buried channel MOSFET transfer characteristics relating the gate (VG), drain (VDD) and source (VS) voltages. For comparison, a surface channel MOSFET without buried channel implant is also shown. Note that the linear range for the surface device is between VS=0.2 /VG=1.0V to VS=2 /VG=3.3V for an overall dynamic range of 1.8V at the source. For the buried channel device operation is from VS=0.9 /VG=0V to VS=3.1 /VG=2.7V for a range of 2.2V. It is important to note that a surface channel device exhibits V/V nonlinearity near full well as the source voltage approaches ground potential. In contrast, a buried channel device shows non linearity for low signal levels unless VG is lowered from 3.3V by adjusting VREF. Figure 58b shows how the threshold shifts with buried channel implant dose (where maximum dose is normalized to unity). Note to stay linear the gate voltage must be reduced as dose increases. For extreme doses dynamic range decreases dramatically. Hence, buried channel optimization must consider trade off’s between surface barrier height for buried operation, V/V nonlinearity and dynamic range.

The buried channel is also used in the pixel’s reset transistor. A standard p-well reset transistor is problematic because the gate drive voltage must be driven ‘hard’ enough to overcome the MOSFETs threshold in taking its source (or sense node) to the drain voltage. Overdriving the reset MOSFET introduces unnecessary reset clock feed through which reduces dynamic range. This problem is particularly important to high V/e- pixels where high reset clock feedthrough is present. Figure 59a shows the sense node response for both buried channel and surface channel reset MOSFETs. Note that the surface device requires reset clock drive of 4V to achieve ‘hard reset’ whereas the buried channel only requires 2.5 V to reach the 3.3V drain voltage. Figure 59b plots the source voltage as a function of VREF with the gate voltage fixed at 3.3V. The buried channel allows the sense node to reach 4.0 V whereas the surface channel is limited to 2.8V. In general, VREF is always adjusted for optimum performance while keeping the drain voltage of the source follower amplifier fixed (VDD=3.3 or 5V depending on the fabrication process employed).

4.3 Fixed Pattern Noise Pixel-to-pixel fixed pattern noise (FPN) associated with CMOS imagers is composed of three main sources; 1) optical sensitivity nonuniformity,7 2). gain nonuniformity and 3). offset nonuniformity. Approximately 1 % sensitivity nonuniformity is measured for CMOS and CCD sensors. For example, a flat field illumination level of 40,000 e- typically generates 400 e- of optical FPN. The second FPN source is associated with gain variation of the pixel’s source follower MOSFET amplifiers a problem primarily related to CMOS imagers (since CCD readout usually involves one output amplifier). Determining pixel-to-pixel gain variance is not a trivial measurement because many amplifiers and samples per amplifier are required. Pixel gain uncertainty is measured by the photon transfer technique and is found theoretically through the relation,7

2 1/ 2 σe−/ DN = K(e − / DN)( ) (8) NPIX where K(e-/DN) is camera sensitivity expressed in electrons/digital number (DN), NPIX is the number of samples taken for each amplifier and σe-/DN is rms e-/DN sensitivity variation. Note that NPIX > 20,000 samples are required to average photon shot noise down to a 1 % measurement accuracy.

Figure 60a plots rms % gain variation for a CMOS test imager as a function of NPIX for 512 pixel amplifiers collecting up to 60,000 samples per amplifier. The figure also shows how gain nonuniformity varies with source follower MOSFET geometry. Note that the curves follow Eq. 8 until pixel gain nonuniformity begins to dominate photon shot noise. Approximately 1 % gain variation is measured for the larger MOSFETs the same value as optical FPN. Both noise sources are limited by manufacture errors in fabricating the pixels.

The third FPN source, offset nonunformity, is also generated by the pixel’s source follower amplifier. This noise is associated with MOSFET threshold voltage variations to approximately 1% from pixel-to-pixel. Offset FPN variance also increases as MOSFET geometry decreases because of fabrication inaccuracies. Figure 60b plots offset noise, in DN units, as a function of MOSFET gate area showing the FPN decrease. Also plotted is offset noise given in electron units. For this MOSFET family offset FPN is at a minimum for a gate area of approximately 4µm2.

The three FPN sources discussed above can be readily removed from CMOS images. Sensitivity and gain noise can be eliminated through flat-fielding.7 Offset noise is removed by aCDS and dCDS signal processing. However, offset FPN may present a fundamental ADC encoding problem to dCDS signal processing as demonstrated in Fig. 61. Shown is 250 e- rms of offset FPN that is being encoded by a 10-bit ADC assuming 2 e- read noise and 2 e-/DN camera gain. As can be seen, FPN consumes nearly all 1024 bits leaving very few bits to encode the actual signal. Also, shown is a 12-bit ADC which has sufficient bits to encode both the FPN and a 7000 e- signal. The offset FPN encoding problem is especially important to 3T and 5T SNAP pixels that must use dCDS to remove reset noise. Hence for these read modes, 14 and 16-bit ADCs are usually employed unless gain switches are incorporated (e.g., Fig. 18).

5. FUTURE DEVELOPMENTS

Characterization of Sandbox V imagers will undoubtedly unveil many new exciting CMOS developments. For example, it is hopeful that substrate bias and buried channel technology can reliably be implemented into future imagers. Even without Sandbox V data a number of prototype CMOS arrays are being designed that take advantage of the high performance developed to this point. For example, a general purpose architecture that closely follows the Minimal Array design philosophy is illustrated in Fig. 62 showing x-y address encoders, pixel drivers, video mux and both aCDS and dCDS buffered outputs. The arrangement is based on a quad pixel format where four outputs are read in parallel. It is also possible to read the entire imager though a single port if desired. The actual array format implemented depends on the pixel size and their number to fit the reticule field before ‘stitching’ is required (limited to approximately 22mm x 22mm). For example, a quad 1k x 1k x 8µm pixel area with support circuitry is possible. A quad 512 x 512 x 16µm pixel 30 Hz imager, another arrangement, is on Sandbox VI with 5TPPD pixels. The imagers assume that pixel clock generation and x-y address logic control is off-chip. This allows the user to have full flexibility in choosing the read mode desired (progressive scan, SNAP, windowing, etc.) and pixel selection (3T, 4T, 5T, 6T). The imager typically uses off-chip, off-the-shelf 14 and 16-bit ADCs (although a 25MHz 12-bit on-chip pipe-line ADC is an optional feature if dynamic range is not an issue). In doing so ADC power dissipation remains off-chip making the detector easier to cool. And for stiff radiation damage environments encountered, ADCs can be ‘spot shielded’ since the imager itself is reasonably rad hard. Today’s commercial ADCs are very compact units that go hand in hand with the imager. For example, Fig. 63 shows a block diagram of a very high speed commercially available 14-bit quad ADC with LVDS interface contained in a small surface mount package (Texas Instruments: ADS 6445-EP).

The architecture in Fig. 63 can be extended to very large stitched arrays as illustrated in Fig. 64 and 65. The design cells for stitching are based on sub 1k x 1k arrays which allows Mk x Nk format imagers (N and M=1,2,3.. ). For example, a 4k x 4k or a 10k x 10k imager can be fabricated using the same reticule set. The question of ‘yield’ for a 100M pixel sensor is always a concern for imagers this large. Our yield experience for very large arrays is only limited to a 9k x 7k CCD imager fabricated at Philips Laboratory two decades ago that produced a few working devices per lot run.10 Also functional backside illuminated 10k x 10k CCD imagers exist today providing evidence that a 100M CMOS imager is possible.11 Studies suggest that CMOS imager yield will be higher than the CCD for three specific reasons. First, CMOS foundries are usually more ‘clean’ than CCD labs involved with fabricating small quantities of scientific CCD arrays where yield has been to some extent a hit and miss game. In contrast, CMOS commercial foundries demand high yield for obvious economic motivations. Millions of wafers are run through CMOS foundries each year maintaining high yield return.

Figure 57a/b. Buried channel current density and potential wells. Figure 58a/b. Surface and buried channel transfer characteristics.

Figure 59a/b. Buried and surface channel reset MOSFETs. Figure 60a/b. Pixel-to-pixel gain and offset FPN.

Figure 61. dCDS offset FPN encoding problem. Figure 62. General CMOS imager architecture for scientific use.

Second, a crucial short that lowers CCD yield is the gate-to-gate short that occurs between two different poly-silicon gate layers. For CMOS imagers, this short is not possible since only one poly layer is utilized in the designs. Third, the substrate short that occurs between a poly gate and the substrate is catastrophic to the CCD (i.e., the device is usually discarded at any magnitude). For CMOS, this short does not seem to exist, at least with the same impact, even though the oxide insulator between the gate and substrate for CMOS is much thinner compared to scientific CCDs. Although not fully understood, the 40-50A oxide layer grown for 0.25 and 0.18 µm 3.3V CMOS processes does not appear to develop lethal shorts because native oxide present does not punch through at low CMOS operating voltages (1.8 and 3.3V). In contrast, CCDs typically rely on a 500-1000 A gate oxides because operating voltages are much higher (up to 25V). Hence, the substrate short that plagues CCDs may not present the same kind of problem to CMOS, possibly providing higher yield return.

The primary CMOS yield problem identified to date are individual dark pixels, dark columns and rows where the video signal is either partially and totally absent. Open via’s and metal shorts and opens are some of the culprits responsible for lowering the yield. However, for most applications this particular problem may be more of a ‘cosmetic’ issue because computer image processing software can usually be applied to remove the artifacts like this. The other noticeable concern for CMOS yield is associated with gate oxide leakage, a characteristic where some ‘weak’ pixels exhibit very high dark current generation. The problem, which may be physically a mild form of a substrate short, can be somewhat rectified by adjusting the clock and bias potentials and cooling the detector. Undoubtedly, there will be new yield surprises when the first 100M CMOS scientific imagers are screened and characterized if that day ever happens.

Figure 66 shows a new class of imagers where digital TDI (dTDI) CMOS and framing pixels are on the same chip. Such an imager is being considered for NASA’s Jupiter mission to Europa. The dTDI section of the sensor reads all rows quickly and repetitively into a buffer memory as the image moves across the field of view. Each row is cumulatively summed within the memory as full frames are readout (as opposed to summing charge on-chip as CCD TDI imagers operate). Digital TDI operation has advantages and disadvantages over analog TDI (aTDI) CCDs. The main advantage for space missions is the inherent radiation hardness that addressable CMOS pixels offer over CCD. For example, the Europa mission is expecting >2 Mrd of ionizing radiation which would play havoc on CCD CTE and operating windows caused by flat-band shift. Second, dTDI imager will not easily saturate since rows are quickly read and reset each time a row is summed in the memory. Third, unlike TDI CCD use, the target can move through the field of view at any angle from vertical except horizontal. Fourth, different color filters over sets of a few rows can achieve near perfect simultaneous color imaging. Fifth, radiation transient events can be subtracted before they are summed in the memory. The main fundamental disadvantage with dTDI is that the read noise increases by the square-root of the number of TDI stages. However, with low noise CMOS this problem may not be a serious issue for most applications.

Figure 63. Quad 14-bit high-speed commercial ADC. Figure 64. Stitched Mk x Nk CMOS imagers (4k x 4k and 10k x 10k).

Figure 65. Stitching design patterns. Figure 66. dTDI and framing CMOS pixels on the same imager.

ACKNOWLEDGMENTS The authors are very appreciative of Arjun Karroy managing all aspects of fabricating our imagers at Jazz Semiconductor. A special thanks goes out to Alfred McEwen of Lunar and Planetary Lab for useful discussions on dTDI imager technology. REFERENCES

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