inter APPLICATION AP-186 NOTE March 1983 © INTEL CORPORATION, 1983 ORDER NUMBER: 210973-001 Intel Corporation makes no warranty for the use of Its products and assumes no responsibility for any errors which may appear In this document nor does It make a commitment to update the Information contained herein Intel retains the right to make changes to these specifications at any time, without notice Contact your local sales office to obtain the latest specifications before placing your order The following are trademarks of Intel Corporation and may only be used to Identify Intel Products BXP, CREDIT, I, ICE, 12 1CE, ICS, IDBP, IDIS, ILBX, 'm, IMMX, Inslte, INTEL, Intel, Intelevlslon, Intellec, Intellgent Identifier'", InteIBOS, Intellgent Programming'", Intelllnk, IOSP, IPDS, IRMS, ISBC, ISBX, ISDM, ISXM, Library Manager, MCS, Megachassls, Micromainframe, MULTIBUS, Multlchannel,M Plug-A-Bubble, MULTI MODULE, PROMPT, Rlpplemode, RMX/80, RUPI, System 2000, and UPI, and the combination of ICE, ICS, IRMX, ISBC, MCS, or UPI and a numerical suffix MDS IS an ordering code only and is not used as a product name or trademark MDS® IS a registered trademark of Mohawk Data SCiences Corporation . • MULTI BUS IS a patented Intel bus. Additional copies of this manual or other Intel literature may be obtained from I ntel Corporation Literature Department 3065 Bowers Avenue Santa Clara, CA 95051 © INTEL CORPORATION, 1983 INTRODUCTION TO THE CONTENTS 80186 MICROPROCESSOR 1. INTRODUCTION..... ............... 1 2. OVERVIEW OF THE 80186 .......... 2 2.1 The CPU ....................... 2 2.2 80186 CPU Enhancements ....... 2 2.3 DMA Unit ....................... 3 2.4 Timers ......................... 3 2.5 Interrupt Controller ............... 3 2.6 Clock Generator ................ 3 2.7 Chip Select and Ready Generation Un~ ........................... 3 2.8 Integrated Peripheral Accessing .. 3 3. USING THE 80186 .................. 4 3.1 Bus Interfacing to the 80186 ...... 4 3.1.1 Overview ................... 4 3.1.2 Physical Address Generation . 5 3.1.3 80186 Data Bus Operation ... 7 3.1.4 80188 Data Bus Operation '" 7 3.1.5 General Data Bus Operation .. 8 3.1.6 Control Si9..l:§Is .............. 9 3.1.6.1 RD and WR ............... 9 3.1.6.2 Queue Status Signals ...... 11 3.1.6.3 Status Lines ............... 11 3.1 .6.4 TEST and LOCK' ........... 11 3.1.7 HALT Timing ................ 12 3.1.8 8288 and 8289 Interfacing ..... 12 3.1.9 Ready Interfacing ............ 13 3.1.10 Bus Performance Issues .... 16 3.2 Example Memory Systems ....... 16 3.2.1 2764 Interface ............... 16 3.2.2 2186 Interface ............... 17 3.2.38203 DRAM Interface ........ 19 3.2.4 8207 DRAM Interface ........ 19 3.3 HOLD/HLDA Interface ........... 21 3.3.1 HOLD Response ............ 21 3.3.2 HOLD/HLDA Timing and Bus Latency ...................... 21 3.3.3 Coming out of hold .......... 23 3.4 Differences Between the 8086 bus and the 80186 Bus .............. 23 4. DMA UNIT INTERFACING ........... 26 4.1 DMA Features .................. 26 4.2 DMA Unit Programming .......... 26 4.3 DMA Transfers .................. 28 4.4 DMA Requests .................. 28 4.4.1 DMA Request timing and latency ...................... 28 4.5 DMA Acknowledge .............. 30 4.6 Internally Generated DMA Requests ...................... 30 4.7 Externally Synchronized DMA Transfers ...................... 30 AFN·21 0973 AP-186 4.7.1 Source Synchronized DMA 6.6.4 iRMX 86 Mode ............... 49 Transfers .................... 30 6.7 Example 8259A/Cascade Mode 4.7.2 Destination Synchronized DMA Interface ....................... 50 Transfers .................... 30 6.8 Example 80130 iRMX 86 Mode 4.8 DMA Halt and NMI .............. 32 Interface ....................... 50 4.9 Example DMA Interfaces ......... 32 6.9 Interrupt Latency ................ 50 4.9.1 8272 Floppy Disk Interface ... 32 7. CLOCK GENERATOR ............... 51 4.9.28274 Serial Communication 7.1 Crystal Oscillator ................ 51 Interface ..................... 34 7.2 Using an External Oscillator ...... 51 5. TIMER UNIT INTERFACING ......... 34 7.3 Clock Generator ................ 52 5.1 Timer Operation ................. 34 7.4 Ready Generation ... : ........... 52 5.2 Timer Registers ................. 34 7.5 Reset .......................... 52 5.3 Timer Events ................... 37 8. CHIP SELECTS .................... 52 5.4 Timer Input Pin Operation ........ 37 8.1 Memory Chip Selects ............ 53 5.5 Timer Output Pin Operation ...... 38 8.2 Peripheral Chip Selects .......... 53 5.6 Sample 80186 Timer Applications . 38 8.3 Ready Generation ............... 53 5.6.1 80186 Timer Real Time Clock. 39 8.4 Examples of Chip Select Usage ... 54 5.6.2 80186 Timer Baud Rate 8.5 Overlapping Chip Select Areas ... 54 Generator .................... 39 9. SOFTWARE IN AN 80186 SYSTEM ... 55 5.6.3 80186 Timer Event Counter ... 39 6. 80186 INTERRUPT CONTROLLER 9.1 S?:~re~ln~t~~I.i~~~i~.n. ~~ ~.n. ~?1.~~ ... 55 INTERFACING ................... 40 9.2 Initialization for iRMX 86 .......... 55 6.1 Interrupt Controller Model ........ 40 9.3 Instruction Execution Differences 6.2 Interrupt Controller Operation .... 40 Between the 8086 and 80186 .... 55 6.3 Interrupt Controller Registers ..... 40 10. CONCLUSiONS ................... 56 6.3.1 Control Registers ............ 40 6.3.2 Request Register ............ 41 6.3.3 Mask Register and Priority Mask Register ..................... 41 APPENDIX A - Peripheral Control 6.3.4 In-Service Register .......... 41 Block ............................ 58 6.3.5 Poll and Poll Status Registers . 42 A.1 Setting the Base Location of the 6.3.6 End of Interrupt Register ..... 42 Peripheral Control Block ........ 58 6.3.7 Interrupt Status Register ..... 43 A.2 Peripheral Control Block Registers 59 6.3.8 Interrupt Vector Register ..... 43 APPENDIX B - Synchronizers ........ 60 6.4 Interrupt Sources ............... 43 B.1 Why Synchronizers Are Required . 60 6.4.1 Internal Interrupt Sources .... 43 B.2 80186 Synchronizers ............ 60 6.4.2 External Interrupt Sources ..... 43 APPENDIX C - 80186 Example DMA 6.4.3 iRMX 86 Mode Interrupt Interface Code ................... 61 Sources ..................... 44 APPENDIX D - 80186 Example Timer 6.5 Interrupt Response ............... 44 Interface Code ................... 64 6.5.1 Internal Vectoring, Master APPENDIX E - 80186 Example Interrupt Mode ........................ 45 Controller Interface Code ......... 68 6.5.2 Internal Vectoring, iRMX 86 APPENDIX F - 80186/8086 Example Mode ........................ 46 System Initialization Code ........ 70 6.5.3 External Vectoring ........... 47 APPENDIX G - 80186 Wait State 6.6 Interrupt Controller External Performance ..................... 72 Connections .................... 47 APPENDIX H - 80186 New 6.6.1 Direct Input Mode ........... 48 Instructions ...................... 76 6.6.2 Cascade Mode .............. 48 APPENDIX I - 80186/80188 6.6.3 Special Fully Nested Mode ... 48 Differences ...................... 78 AFN-21 0973 inter AP-186 on a single chip (see Figure I), system construction is 1. INTRODUCTION simplified since many of the peripheral interfaces are in­ As state of the art technology has increased the number tegra ted on to the device. of transistors possible on a single integrated circuit, The 80186 family actually consists of two processors: the these devices have attained new, higher levels of both 80186 and 80188. The only difference between the two performance and functionality. Riding this crest are the processors is that the 80186 maintains a 16-bit external Intel 80186 and 80286 microprocessors. While the data bus while the 80188 has an 8-bit external data bus. 80286 has added memory protection and management Internally, they both implement the same processor with to the basic 8086 architecture, the 80186 has integrated the same integrated peripheral components. Thus, ex­ six separate functional blocks into a single device. cept where noted, all 80186 information in this note also The purpose of this note is to explain, through example, applies to the 80188. The implications of having an 8-bit the use of the 80186 with various peripheral and mem­ external data bus on the 80188 are explicitly noted in ap­ ory devices. Because the 80186 integrates a DMA unit, pendix I. Any parametric values included in this note are timer unit, interrupt controller unit, bus controller unit taken from the iAPX 186 Advance Information data and chip select and ready generation unit with the CPU sheet, and pertain to 8Mhz devices. INT3/1NTAI INT2/11'1fAii CLKOUT Vee GND INTI TMR OUT 1 TMR OUT 0 TMR IN t TMR IN t rlD~ ~ 1 Nil INITO ,1 ,~ 'ExECUTIoN iiNiT1 PROGRAMMABLE I I ~ ~ TIMERS X, X, I 0 1 2 16-81T I MAX COUNT ~~ ALU PROGRAMMABLE REGISTER B ~1. I INTERRUPT CLOCK I CONTROLLER MAXCQUNT GENERATOR REGISTER A 16-81T I GENERAL I CONTROL REGISTERS PURPOSE REGISTERS I CONTROt I 16-81T -.J REGISTERS COUNT REGISTER r {'[ { { INTERNAL BUS DRQO .-1- DRQl J U U PROGRAMMABLE+ ~ DMAUNIT c- O 1 CHIP·SELECT 20·BIT SRDY'-I- UNIT SOURCE POINTERS AROY -I- BUS INTERFACE 20·BIT IS-BIT TEST -I- UNIT L) DESTINATION HOLD SEGMENT POINTERS '-I- REGISTERS HLDA,"-f- PROGRAMMABLE 16·61T 6-BYTE CONTROL I RES,-I- PREFETCH TRANSFER COUNT RESET '--f- QUEUE REGISTERS 11 CONTROL REGISTERS I III {}JJ ~DiN l~AtE ucs _ 1_ PCS6/A2~ LOCK RD ADO- AI6/S3- ±t LCS PCSS/Al ADIS A19/S6 DT/A BHE/S7 MCS0-3 PCSO-' Figure 1. 80186 Block Diagram AFN·210973 AP·186 2. OVERVIEW OF THE 80186 wealth of conditional branch and other control instructions. 2.1 The CPU In the 80186, as in the 8086, instruction fetching and in­ struction execution are performed by separate units: the The 80186 CPU shares a common base architecture bus interface unit and the execution unit, respectively. with the 8086, 8088 and 80286. It is completely object The 80186 also has a 6-byte prefetch queue as does the code compatible with the 8086/88. This architecture 8086. The 80188 has a 4-byte prefetch queue as does the features four 16-bit general purpose registers (AX,BX, 8088. As a program is executing, opcodes are fetched CX,DX) which may be used as operands in most arith­ from memory by the bus interface unit and placed in this metic operations in either 8 or 16 bit units.