CPU and Memory Lecture 3 Hierarchical Structure Application level language: “get the average in final” High level language: C/C++ A=(B1+B2+…+BN)/N Low level language: assembly (add, sub, clr) Binary Instruction Codes Human-readable HARDWARE representation ofbif binary inst ruc tion co de Lecture 3 2 1 Von Neumann Machine Storing both programs and data in the same memory unit: - simple architecture CPU - possibility to process programs as data - allows for self-modifying Address Bus Data Bus programs Port: Point at which information enters/leaves the computer Bus: paths along which signals flow I/O Memory Disadvantage of this architecture: (data - computer performance is limited port) by the necessity to pass all program and data over the relatively restricted number of wires on the bus Lecture 3 3 Memory Input: n Binary Bits: (An-1,An-2, • • • • • A0) 23 0 Control signals 4 1 read 12 2 address write 3 … 9 … data Input/Output: data m Binary Bits: (Dm-1,Dm-2, • • • • • D0) Lecture 3 4 2 Memory and CPU address address Address path Central Memory Processing -instructions Unit -data -CPU data data Data path Lecture 3 5 Von Neumann Machine (pseudocode) I := 0 REPEAT get an instruction from memory location I execute the instruction I := I + 1 FOREVER Lecture 3 6 3 Von Neumann Machine (pseudocode) I := 0 REPEAT get an instruction from memory location I execute the instruction: decode the instruction IF instruction requires data THEN fetch data perform operation defined by instruction IF instruction requires data to be stored THEN store data in memory I := I + 1 FOREVER Lecture 3 7 Instruction: C := A+ B Memory instruction C:=A+B read Central Processing Unit address -CPU of data A read B read C write data used result Lecture 3 8 4 Simplified Structure of a CPU Program Counter PC 01 Memory address register 0 MAR 1 Incrementer +1 0 address Memory 0: AB CD data Instruction Register Op-code AB address CD Memory Buffer Register AB CD Address register(s) Control Data register(s) unit ALU (Arithmetic & Logic Unit) Address path Data path Lecture 3 9 Simplified Structure of a CPU Memory Address Register – holds the address of the next location in memory to be accessed Memory Buffer Register – holds the data just read from the memory, or the data to be written into it Program Counter – contains the address of the next instruction to be executed Lecture 3 10 5 Simplified Structure of a CPU Instruction Register – holds the most recently read instruction from the memory Data Register(s) – general purpose register(s) that holds data Address Register(s) – register(s) that holds addresses Arithmetic and Logic Unit – calculates a function of one or two inputs, the actual function is determined by the bit pattern of the instruction in the instruction register Lecture 3 11 Simplified Structure of a CPU Control unit – interprets the instruction in the instruction register, it is responsible for converting the bit pattern of an instruction into the sequence of actions necessary to execute the instruction Lecture 3 12 6 Simplified Structure of a CPU: Registers vs. Memory Registers are located within the CPU and can be accessed “immediately”. Memory is external to the CPU and are accessed by a 16- bit to 64-bit address. DtData in reg itisters: money in your poc ktket Data in memory: money in your bank Lecture 3 13 Notation: Register Transfer Language - RTL Square brackets – contents of the register (or the memory location) For example, [MAR] is interpreted as “the contents of the memory address register” [MAR] = 3 Lecture 3 14 7 RTL Notation - Cont. Normal brackets “ ( ) “ – indicate a location within memory In this case, M(address) is interpreted as the memory location with the address “address” M(100): the memory location with address 100 [M(100)]: the content of the memory location with address 100. So [M(100)] =5. 100 5 101 6 102 11 Lecture 3 15 RTL Notation (cont.) Transfer of information between registers (or memory locations) is idiindicate dbd by t he bac kwar d arrow: ← For example: [PC] ← 4 [M(R)] ← [M(P)] + [M(Q)] 4 PC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Lecture 3 16 8 Executing an Instruction Fetching an instruction: step 1 [mar] [pc] Program Counter PC Memory address register MAR address Incrementer Memory data Instruction Register Op-code address Memory Buffer Register Address register(s) Control Data register(s) unit ALU (Arithmetic & Logic Unit) Lecture 3 17 Executing an Instruction Fetching an Instruction: step 2 [pc][pc]+1 Program Counter PC Memory address register MAR address Incrementer Memory data Instruction Register Op-code address Memory Buffer Register Address register(s) Control Data register(s) unit ALU (Arithmetic & Logic Unit) Lecture 3 18 9 Executing an Instruction Fetching an Instruction: step 3 [mbr][M([mar])] Program Counter PC Memory address register MAR D=[MAR] address Incrementer Memory data Instruction Register [M(D)] Op-code address Memory Buffer Register Address register(s) Control Data register(s) unit ALU (Arithmetic & Logic Unit) Lecture 3 19 Executing an Instruction FETCH [mar] ← [pc] send instr addr to MAR [pc] ← [pc] + 1 point to next instr [mbr] ← [m(()[mar])] read instr [ir] ← [mbr] copy instr to IR Lecture 3 20 10 Executing an Instruction Execution of ADD P, D0 Program Counter PC Memory address register MAR address Incrementer Memory data Instruction Register Content of memory P Op-code address Memory Buffer Register Add something to D0 addr. of something Address register(s) Control Data register(s) unit ALU (Arithmetic & Logic Unit) Lecture 3 21 Executing an Instruction ADD P, D0: [d0] ← [d0] + [M(P)] [mar] ← [IR(addr_field)] send operand address to MAR [mbr] ← [M([mar])] read operand [d0] ← [d0] + [mbr] perform addition Lecture 3 22 11.