Overview ° Intro to Computer Architecture (30 minutes) CS152 ° Administrative Matters (5 minutes) Computer Architecture and Engineering Lecture 1 ° Course Style, Philosophy and Structure (15 min) ° Break (5 min) Introduction and Five Components of a Computer ° Organization and Anatomy of a Computer (25) min) CS152 / Spring 2002 Lec2.2 Lec1.1 What is “Computer Architecture” Instruction Set Architecture (subset of Computer Arch.) ... the attributes of a [computing] system as seen by Computer Architecture = the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization Instruction Set Architecture + of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964 Machine Organization + ….. -- Organization of Programmable SOFTWARE Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions Lec2.3 Lec2.4 Computer Architecture’s Changing Definition The Instruction Set: a Critical Interface ° 1950s to 1960s: Computer Architecture Course: Computer Arithmetic ° 1970s to mid 1980s: Computer Architecture Course: software Instruction Set Design, especially ISA appropriate for compilers ° 1990s: Computer Architecture Course: instruction set Design of CPU, memory system, I/O system, Multiprocessors, Networks hardware ° 2000s: Computer Architecture Course: Non Von- Neumann architectures, Reconfiguration, Focused MIPs Lec2.5 Lec2.6 Example ISAs (Instruction Set Architectures) MIPS R3000 Instruction Set Architecture (Summary) Registers ° Digital Alpha (v1, v3) 1992-97 ° Instruction Categories • Load/Store R0 - R31 ° HP PA-RISC (v1.1, v2.0) 1986-96 • Computational ° Sun Sparc (v8, v9) 1987-95 • Jump and Branch • Floating Point ° SGI MIPS (MIPS I, II, III, IV, V) 1986-96 - coprocessor PC • Memory Management ° Intel (8086,80286,80386, 1978-96 HI 80486,Pentium, MMX, ...) • Special LO 3 Instruction Formats: all 32 bits wide OP rs rt rd sa funct OP rs rt immediate OP jump target Lec2.7 Q: How many already familiar with MIPS ISA? Lec2.8 Organization The Big Picture ° Capabilities & Performance Logic Designer's View ° Since 1946 all computers have had 5 components Characteristics of Principal Functional Units ISA Level • (e.g., Registers, ALU, Shifters, Logic Units, ...) FUs & Interconnect Processor ° Ways in which these components Input are interconnected Control ° Information flows between Memory components ° Logic and means by which such Datapath information flow is controlled. Output ° Choreography of FUs to realize the ISA ° Register Transfer Level (RTL) Description Lec2.9 Lec2.10 Example Organization What is “Computer Architecture”? ° TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 Application Operating MBus Module System SuperSPARC Compiler Firmware Floating-point Unit Instruction Set Architecture Instr. Set Proc. I/O system L2 CC DRAM Integer Unit $ MBus Controller Datapath & Control Digital Design L64852 MBuscontrol Circuit Design Inst Ref Data M-S Adapter Layout Cache MMU Cache STDIO SBus serial kbd ° Coordination of many levels of abstraction Store SBus SCSI mouse Buffer DMA Ethernet audio ° Under a rapidly changing set of forces RTC Bus Interface SBus Boot PROM ° Design, Measurement, and Evaluation Cards Floppy Lec2.11 Lec2.12 Forces on Computer Architecture Technology DRAM chip capacity Microprocessor Logic Density DRAM 100000000 Year Size Technology Programming 10000000 1980 64 Kb R10000 Languages Pentium 1983 256 Kb R4400 1000000 i80486 1986 1 Mb uP-Name i80386 Applications Transistors i80286 1989 4 Mb 100000 R3010 Computer 1992 16 Mb SU MIPS Cleverness i8086 i80x86 M68K 10000 Architecture 1996 64 Mb MIPS Alpha 1999 256 Mb i4004 1000 2002 1 Gb 1965 1970 1975 1980 1985 1990 1995 2000 2005 Operating ° In ~1985 the single-chip processor (32-bit) and the Systems single-board computer emerged History • => workstations, personal computers, multiprocessors have been riding this wave since ° In the 2002+ timeframe, these may well look like mainframes compared single-chip computer Lec2.13 (maybe 2 chips) Lec2.14 Technology => dramatic change Performance Trends ° Processor • logic capacity: about 30% per year • clock rate: about 20% per year Supercomputers ° Memory Mainframes • DRAM capacity: about 60% per year (4x every 3 years) Minicomputers • Memory speed: about 10% per year • Cost per bit: improves about 25% per year ° Disk Microprocessors • capacity: about 60% per year Log of Performance • Total use of data: 100% per 9 months! ° Network Bandwidth Year • Bandwidth increasing more than 100% per year! 1970 1975 1980 1985 1990 1995 Lec2.15 Lec2.16 Applications and Languages Computers in the News: Sony Playstation 2000 ° CAD, CAM, CAE, . ° Lotus, DOS, . ° Multimedia, . ° The Web, . ° JAVA, . ° The Net => ubiquitous computing ° ??? ° (as reported in Microprocessor Report, Vol 13, No. 5) • Emotion Engine: 6.2 GFLOPS, 75 million polygons per second • Graphics Synthesizer: 2.4 Billion pixels per second • Claim: Toy Story realism brought to games! Lec2.17 Lec2.18 Input Input Where are we going?? Multiplicand Multiplier CS152: Course Content 32 Multiplicand Register LoadMp 32=>34 signEx 32 <<1 34 34 Arithmetic 32=>34 1 0 signEx 34x2 MUX Multi x2/x1 Single/multicycle 34 34 34-bit ALU Sub/Add Control Computer Architecture and Engineering Logic 34 Datapaths 32 2 32 ShiftAll "LO[0]" ENC[2] 2 bits Extra LO[1] Encoder Booth 2 HI register 2 LO register Prev ENC[1] (16x2 bits) (16x2 bits) ENC[0] 2 LO[1:0] LoadHI ClearHI LoadLO 32 32 Result[HI] Result[LO] Instruction Set Design Computer Organization 1000 µProc CPU 60%/yr. Interfaces Hardware Components (2X/1.5yr) “Moore’s Law” 100 Processor-Memory Performance Gap: CS152 (grows 50% / year) Compiler/System View Logic Designer’s View 10 DRAM Performance 9%/yr. DRAM (2X/10 yrs) 1 •“Building Architect” •“Construction Engineer” IFetch Dcd Exec Mem WB Spring ‘99 1984 1997 1999 1980 1981 1982 1983 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1998 2000 IFetch Dcd Exec Mem WB Time IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Pipelining À I/O Memory Systems Lec2.19 Lec2.20 CS152: So what's in it for me? Conceptual tool box? ° Evaluation Techniques ° In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs ° Levels of translation (e.g., Compilation) present at the hardware/software boundary. ° Levels of Interpretation (e.g., Microprogramming) • Insight into fast/slow operations that are easy/hard to implementation hardware ° Hierarchy (e.g, registers, cache, mem,disk,tape) • Out of order execution and branch prediction ° Pipelining and Parallelism ° Experience with the design process in the context of ° Static / Dynamic Scheduling a large complex (hardware) design. ° Indirection and Address Translation • Functional Spec --> Control & Datapath --> Physical implementation ° Synchronous and Asynchronous Control Transfer • Modern CAD tools ° Timing, Clocking, and Latching ° Designer's "Conceptual" toolbox. ° CAD Programs, Hardware Description Languages, Simulation ° Physical Building Blocks (e.g., CLA) ° Understanding Technology Trends Lec2.21 Lec2.22 Course Structure Typical Lecture Format ° Design Intensive Class --- 75 to 150 hours per semester per student ° 20-Minute Lecture MIPS Instruction Set ---> Standard-Cell implementation ° 5- Minute Administrative Matters ° Modern CAD System : ° 25-Minute Lecture Schematic capture and Simulation ° 5-Minute Break (water, stretch) Design Description Computer- based "breadboard" • Behavior over time ° 25-Minute Lecture • Before construction ° Instructor will come to class early & stay after to ° Lectures (rough breakdown): answer questions • Review: 2 weeks on ISA, arithmetic • 1 1/2 weeks on technology, HDL, and arithmetic • 3 1/2 weeks on standard Proc. Design and pipelining Attention • 2 weeks on DSP and Low Power Issues • 2 weeks on memory and caches • 1 1/2 weeks on Memory and I/O 20 min. Break 25 min. Break 25 min. “In Conclusion, ...” • 2 weeks exams, presentations Time Lec2.23 Lec2.24 Course Administration Course Exams ° Instructor: Bob Brodersen (rb@eecs) 402 Cory Hall °Reduce the pressure of taking exams Office Hours(Tentative): Mon 10:30-12:00 • Midterms: (approximately) March 5 and May 2 ° TAs: Ed Liao ([email protected]) • 3 hrs to take 1.5-hr test (5:30-8:30 PM, 306 Soda). • Our goal: test knowledge vs. speed writing ° Labs: UNIX accounts on Soda machines NT accounts in 119 Cory • Both mid-terms can bring summary sheets ° Materials: http://bwrc.eecs.berkeley.edu/classes/cs152 ° Newsgroup: ucb.class.cs152 ° Text: Computer Organization and Design: The Hardware/Software Interface, Second Edition, Patterson and Hennessy • Q: Need 2nd Edition? yes! >> 50% text changed, all exersizes changed all examples modernized, new sections, ... Lec2.25 Lec2.26 Course Workload Homework Assignments and Project ° Most assignment consists of two parts ° Reasonable workload (if you have good work habits) • Individual Effort: Exercises from the text book • No final exam: Only 2 mid-terms • Team Effort: Lab assignments • Every lab feeds into the project • First Homework: out Thursday on Website. • Project teams have 4 or 5 members ° Assignments (usually) go out on Tuesday ° Spring 1995 HKN workload survey • Exercises due on a later Tuesday at beginning of lecture (1 to 5, 5 being hardest) - Brief (15 minute) quiz on assignment material in lecture CS 150 4.2 CS 164 3.1 - Must understand assignment