View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by ePublications DESIGN AND IMPLEMENTATION OF FPGA BASED SOFTWARE DEFINED RADIO USING SIMULINK HDL CODER Dr. Hikmat N. Abdullah B.Sc. Hussein A. Hadi [email protected] [email protected] University of Al-Mustansiryah, College of Engineering, Electrical Engineering Department, Baghdad-Iraq. ABSTRACT: are hardware defined with little or no This paper presents the design software control; they are fixed in function procedure and implementation results of a for mostly consumer items for broadcast proposed software defined radio (SDR) reception. They have a short life and are using Altera Cyclone II family board. The designed to be discarded and replaced [1]. implementation uses Matlab/SimulinkTM, Over the last few years, analog radio Embedded MatlabTM blocks, and Cyclone II systems are being replaced by digital radio development and educational board. The systems for various radio applications in design has first implemented in military, civilian and commercial spaces. In Matlab/SimulinkTM environment. It is then addition to this, programmable hardware converted to VHDL level using Simulink modules are increasingly being used in HDL coder. The design is synthesized and digital radio systems at different functional fitted with Quartus II 9.0 Web Edition® levels. Commercial wireless communication software, and downloaded to Altera Cyclone industry is currently facing problems due to II board. The results show that it is easy to constant evolution of link-layer protocol develop and understand the implementation standards (2.5G, 3G, and 4G), existence of of SDR using programmable logic tools. incompatible wireless network technologies The paper also presents an efficient design in different countries inhibiting deployment flow of the procedure followed to obtain of global roaming facilities and problems in VHDL netlists that can be downloaded to rolling-out new services/features due to FPGA boards. wide-spread presence of legacy subscriber handsets [2]. KEYWORDS: FPGA, Embedded Matlab, The solution of above big problems software defined radio. can be solved by using the software defined radio (SDR), which comprised of both 1. INTRODUCTION: software and hardware, it use a The twentieth century saw the reprogrammable ability of field explosion of hardware defined radio (HDR) programmable gate array (FPGA) or digital as a means of communicating all forms of signal possessor (DSP) to built an open audible; visual, and machine-generated architecture with software implementation information over vast distances. Most radios of radio frequencies such as 15 modulation/demodulation, coding/decoding, development. Using the coder, system ..etc[3]. architects and designers can spend more SDR in a few words is a radio that time on fine-tuning algorithms and models promises to solve the gap between link-layer through rapid prototyping and protocol standards and provide a quick experimentation and less time on HDL solution of global roaming problems by coding. Simulink HDL coder compatibility building generic platform that switches its checker utility can be run to examine functionalities by using software control. In MATLAB-Simulink model semantics and this work, an efficient short cycle design blocks for HDL code generation flow has been proposed. With this design compatibility, then by invoking the coder, flow, the designer could implement his using either the command line or the design models originally written as Matlab graphical user interface. codes or simulink blocks using FPGA board The coder generates VHDL or without the need to learn VHDL or even Verilog code that implements the design other FPGA design entries. As well as, this embodied in the model. Usually, a approach reduces the time required to corresponding test bench also can be complete the hardware implementation. It generated. The test bench with HDL will give the beginner designer, for instance simulation tools can be used to drive the the student, a better and easy understanding generated HDL code and evaluate its of how different design parts behave using behavior. The coder generates scripts that his/her written Matlab codes/simulink automate the process of compiling and blocks. However, the automatic translation simulating your code in these tools. EDA of Matlab code/simulink blocks to VHDL Simulator Link™ MQ, EDA Simulator Link one requires extra requirements. The written IN or EDA Simulator Link DS software can Matlab code/simulink blocks should take be used from the MathWorks™ to into ahead what is so called fixed point cosimulate generated HDL entities within a arithmetic notations (Embedded MatlabTM Simulink model. [4]). In this work, the EDA Simulator Link™ MQ are used but in another easily 2. Generation of VHDL Codes for way which can be followed by invoke the MATLAB-Simulink Models: ModelSim manually. The test bench feature The algorithms and designs used to increases confidence in the correctness of define systems are normally modeled using the generated code and saves time spent on high level software languages like test bench implementation. The design and MATLAB, MATLAB-Simulink or C. But test process is fully iterative. At any point, these designs could not be suited to real the designer can return to the original model, hardware. Simulink HDL coder [5] is a new make modifications, and regenerate code. tool, which comes with MATLAB-Simulink When the design and test phases of the software package and can be used to project have been completed, easily the generate hardware description language generated HDL code can be exported to (HDL) code based on Simulink® models synthesis and layout tools for hardware and Stateflow® finite-state machines. The realization. The coder generates synthesis coder brings the Model-Based Design scripts for the Synplify® family of synthesis approach into the domain of application- tools. specific integrated circuit (ASIC) and field The procedure followed to obtain programmable gate array (FPGA) VHDL netlists that could be downloaded to 16 FPGA boards could be summarized in the Some MATLAB-Simulink blocks, flow chart shown in Fig.1. especially those contain complex functions like encoders/decoders, modulators/ demodulators, ..etc. could not be converted start to VHDL codes. To solve this problem, these blocks are redesigned using their basic designing MATLAB-models with blocks supported components such that it could be converted by Simulink HDL coder to VHDL codes. Fig.2 shows the designed SDR system using MATLAB-Simulink blocks Setting up Simulink HDL coder configuration supported by the HDL coder while Figs.3 and 4 show further details of the blocks in Fig.2. Fig.5 shows that the transceiver part Setting up model parameters with the HDL coder in Fig.3 which consists of two branches, each branch support a different type of Generating HDL entities for model blocks modulation scheme while the coding scheme used is convolutional code. The control circuit of Fig.3 can be used to decide which Manual modification of VHDL codes generated (if transceiver is on and the other is off: when necessary) the input1 of the control circuit is 0, the lower branch will turns on while the upper Creating test bench for simulation purposes branch will turns off. The opposite thing happend when input1 is decided as logic one. Exporting VHDL netlists to Quartus and test The modulators/demodulators in benches to Modelsim Fig.4 have been designed using embedded MATLAB functions (m-files) while other Verifying design functionality blocks designed by MATLAB-Simulink (ModelSim tool) blocks supported by Simulink HDL coder. For example, Fig.5 shows the implementation of convolutional encoder. In 2.1 DesignDesign of Simulink synthesis using models QuartusII with blocks Fig.5, a convolutional encoder of rate 1/2 with constraint length 7 and code array 171 Downloading bit stream file to FPGA board and 133 is used [6]. The constraint length denotes the number of shift registers over, which the modulo-2 sum of the input data is End performed. The rate 1/2 signifies that for every 1 bit input, the encoder will output 2 encoded bits. Viterbi decoder is used to Fig.1 design flow for realizing MATLAB- decode the convolutionally encoded signal Simulink models using FPGA boards. by finding an optimal path through all the possible states of the encoder [7]. 2.1 Design of Simulink Models with There are two steps in the decoding Blocks Supported by Simulink HDL process. The first step is to weigh the cost of Coder: incoming data against all possible data input combinations. Either a Hamming or 17 Fig.2 The designed SDR receiver using MATLAB-Simulink blocks supported by Simulink HDL coder. Fig.3 The details of SDR block in Fig.2 Fig.4 further detail of the transceiver construction 18 Fig.5 Implementation of the convolutional encoder using MATLAB-Simulink blocks supported by HDL coder. Euclidean metric may be used to determine with the Mentor Graphics® ModelSim® the cost[8]. The second step is to traceback HDL simulator and with Synplicity® through the trellis and determine the Synplify® synthesis software. By overriding optimal path. The length of the trace through script generation defaults, Simulink HDL the trellis can be controlled by the traceback Coder can programed to generate scripts for length parameter [8]. The constraint length most EDA tools. EDA script generation can of 7 and the code array 171 and 133 used for be customized via the Simulink HDL Coder decoding are the same as in convolutional GUI, or by setting makehdl or makehdltb encoder. The traceback length parameter, properties at the command line, or in a that is, the number of trellis states processed control file. before the decoder makes a decision on a bit, In this work, the ModelSim-Altera is set to 34. The decoder outputs the data 6.4a Starter Edition package as simulator bits which are later grouped accordingly.