Workshop Proposal Organizer(s) Name: FERRARI Philippe Name: GAQUIERE Christophe Affiliation: RFIC-Lab University Grenoble Affiliation: IEMN, University of Lille, France Alpes, France Email: [email protected] Email: [email protected] lille1.fr Workshop Title: Recent Advances in SiGe BiCMOS: Technologies, Modelling and Circuits for 5G, radar and imaging Topic: mm-wave integrated circuits Workshop Abstract (the abstract should be between a quarter and half a page long in font size 10, single column, about 1500 to 3000 characters with spaces): In this workshop, the recent advances in SiGe BiCMOS technology for mm-wave applications will be illustrated by many examples of technology development, designs, from components to circuits and systems. The SiGe BiCMOS most advanced technologies in Europe will first be presented, from STMicroelectronics, Infineon and IHP. In particular, the last advances concerning 푓푚푎푥/푓푡 frequencies will be highlighted. SiGe technology will be compared to standard advanced CMOS technologies to highlight the advantages/drawbacks of each technology family. Next, specific characterization techniques for frequencies in mm-wave range will be presented, from small- (linear) to large signal (nonlinear) conditions. Some examples of components compact modelling will be illustrated. High-frequency and low-frequency noise issues, along with ageing issues, will also be addressed. Then, circuit and system level presentations will highlight design techniques in SiGe BiCMOS technologies. Circuits and systems addressing many different frequencies will be presented, for 5G applications (28 GHz and 60 GHz), back-hauling and automotive radars in E-band, and future applications like imaging above 100 GHz, with several designs at 120-140 GHz and 300 GHz, respectively. In particular, beam-forming applications, which is a hot topic today for future point to point communications systems, will be developed. As for the technologies, circuit- and system-level comparison will also be carried out between SiGe BiCMOS and standard CMOS (including FDSOI), to highlight pro & cons of each technology. Important Information - Accepted workshops will be scheduled to one of the workshops days of the EuMW 2019 week. The assignment of the workshops in a given day will be conducted to satisfy the planning constraints. Hence, organizers are expected to inform their speakers accordingly. - Workshop fee waivers will be granted to the workshop organizers (two maximum) and workshop speakers (one per presentation) upon reception of the presentation slides (1 color slide per A4 page in pdf format) before the deadline 5th July 2019. The fee waivers are not guaranteed once the deadline has passed. - Please note that, in this case, the fee waiver applies ONLY to the specific workshop and NOT to other events taking place during the week, therefore: Workshop speakers and workshop organizers must register and pay the fees for the other events they wish to attend (EuMC, EuMIC, EuRAD, conferences, WS, SC, …). I have read and understood the above important information and transmitted this information to all the Speakers who also understood: Yes Complete the rest of the form only if your answer to the above question is Yes. 2 Speakers 1. Speaker's Name: Pascal CHEVALLIER Confirmed: yes Affiliation: STMicroelectronics Presentation Title: Towards 600 to 700 GHz fMAX SiGe BiCMOS platforms in Europe Speaker’s Email: [email protected] Abstract: Most advanced BiCMOS technologies exhibit +500 GHz fMAX SiGe HBTs in 0.13-µm CMOS and ~400 GHz in 90- nm and 55-nm CMOS, while a 720 GHz fMAX HBT, not compatible with CMOS, was demonstrated. This talk will present the process developments work done in Europe by IHP, Infineon Technologies and STMicroelectronics in the frame of TARANTO European project, with the objective to maintain Europe at the forefront of BiCMOS by developing nanoscale platforms targeting 600 GHz fMAX SiGe HBTs and to evaluate the feasibility of integrating a 700 GHz fMAX HBT in CMOS. This encompasses research activities on advanced transistor architectures, related process steps, and bipolar / CMOS integration schemes. The investigated CMOS nodes go from 0.13-µm bulk to 28-nm FD-SOI. 600-GHz fMAX 90-nm and 55-nm BiCMOS platforms from Infineon Technologies and STMicroelectronics, respectively, are available for circuits design. In addition feasibility of advanced CMOS / BiCMOS heterogeneous integration will be discussed. 2. Speaker's Name: Ned CAHOON Confirmed: yes Affiliation: Global Foundry, Germany Presentation Title: Silicon Technologies for mm-Wave Applications Speaker’s Email: [email protected] Abstract: The mm-Wave era is upon us and opens up many opportunities for differentiated silicon Integrated Circuit technologies including SiGe BiCMOS, Partially-Depleted (PD) SOI and Fully-Depleted (FD) SOI. In addition to the requisite high transistor ft/fmax needed for operation at mm-Wave frequencies, each of these technologies has unique attributes and strengths that have been optimized for specific application requirements and can be leveraged to provide a solution advantage. In this talk, we will discuss the application requirements and technology trade-offs for several mm-Wave applications of interest, including 5G, mm-Wave imaging, broadband satellite communications and ADAS radar. 3 3. Speaker's Name: Sébastien FREGONESE Confirmed: yes Affiliation: University of Bordeaux Presentation Title: On-wafer small signal characterization beyond 100GHz for compact model assessment Speaker’s Email: [email protected] Abstract: The presentation about “On-wafer small signal characterization beyond 100GHz for compact model assessment” will give an overview about different issues that may arise when facing high frequency S-parameter measurements, such as: Test structures design for on-wafer TRL, design of de-embedding structures Benchmark of off-wafer SOLT vs on-wafer TRL Investigation of GSG-probe design Analysis of coupling with neighbor structures Band continuity investigation Application to HBT measurements up to 500 GHz The talk will conclude with a comparison of measurements to the HiCuM compact model with emphasis on NQS effects. 4. Speaker's Name: Christophe GAQUIERE Confirmed: yes Affiliation: University of Lille Presentation Title: Noise and power characterization in mm-wave and sub mm-wave frequencies Speaker’s Email: [email protected] Abstract: 5. Speaker's Name: Sorin P. VOINIGESCU Confirmed: yes Affiliation: University of Toronto Presentation Title: Design Techniques and Technologies for Next Generation Fiberoptics Systems and High Temperature (> 10 K) Quantum Processors. Speaker’s Email: [email protected] 4 Abstract: The next generation of 128 Gbaud fiberoptic circuits, instrumentation and high-temperature quantum computing processors will require transistor technologies with adequate power gain beyond 300 GHz. In this presentation I will compare SiGe BiCMOS, 22nm FDSOI CMOS and InP HBT technology performance and 100+GS/s DACs and ADCs in these technologies. Finally, I will discuss the need for a SiGe BICMOS technology with 700+ GHz fMAX SiGe HBTs and the most aggressively scaled (< 12nm) FDSOI MOSFETs. 6. Speaker's Name: Cristell MANEUX Confirmed: yes Affiliation: University of Bordeaux Presentation Title: Advances in Aging Compact Model for Hot Carrier Degradation in SiGe HBTs under Dynamic Operating conditions for reliability-aware circuit design Speaker’s Email: [email protected] Abstract: Aggressive miniaturization of SiGe heterojunction bipolar transistors (HBTs) has enhanced the frequency performance of the transistors while sacrificing on the operating current density and breakdown voltages. This has posed as a major concern in terms of long-term reliability since modern transistors are required to operate closer and even beyond their safe-operating areas. One of these reliability issues is hot-carrier degradation that predominantly limits the lifetimes of modern SiGe HBTs, the underlying mechanism of which is trap generation at the emitter-base spacer oxide interface through Si-H bond-breaking followed by non-ideal base current degradation. Generation of interface traps can be correctly described by reaction–diffusion (R-D) model for long-term aging. Besides, the analytic form of R-D model is quite suitable for circuit design while preserving the physical basis of degradation. In compact model implementation, an approximate solution of the R-D rate equation is commonly used in which the time-dependence of the degradation is governed by a power law (~tn). Though it offers simplicity, this power law does neither account for the saturation of the degradation characteristics after long-term aging (when the trap density approaches the total number of available dangling bonds), nor for the initial phase when the generation process dominates (~t). To circumvent specific limitations of these models, the presentation will discuss a complete analytical solution of the R-D model, which captures all phases of degradation in one single analytic form, thus enabling physics- based compact modelling owing to its design-friendly implementation. This compact model also takes into account for the dynamic stress condition, i.e., the invariance in time is ensured for the degradation under variable stress conditions. The model implementation is proposed to account for dynamic stress conditions, while featuring the same R-D model framework. The presentation