CHAPTER 9 THE CONTROL UNIT 285 THE CONTROL UNIT 9 9.1 A Microarchitecture for the ARC The microarchitecture of a computer implements the fetch-execute cycle. As we see in Chapter 4, the steps involved in the fetch-execute cycle are: 1) Fetch an instruction from main memory. 2) Decode the opcode. 3) Read operand(s) from main memory, if any. 4) Execute the instruction and store results. 5) Go to Step 1. The microarchitecture fetches the next instruction to be executed, determines which instruction it is, fetches the operands, and finally executes the instruction. The microarchitecture consists of a data section that contains registers and an ALU, and a control section, as illustrated in Figure 9-1. The data section is also referred to as the datapath. The control section can be implemented in a hard- wired form, using the digital design methods covered in Appendix A, or it may be driven by a microprogram, which is an internal program that is not visible to the user. For the moment, we will consider a microprogrammed approach for the ARC architecture. The instruction set and instruction format for the ARC subset is repeated from Chapter 4 in Figure 9-2. There are 15 instructions that are 286 CHAPTER 9 THE CONTROL UNIT Registers Control Unit ALU Datapath Control Section (Data Section) System Figure 9-1 High level view of a microarchitecture. grouped into four formats according to the leftmost two bits of the coded instruction. The Processor Status Register %psr is also shown. 9.1.1 THE DATAPATH A datapath for an example ARC implementation is illustrated in Figure 9-3. The datapath contains 32 user-visible data registers (%r0 – %r31), the program counter (%pc), four temporary registers (%temp0 – %temp3), the instruction register (%ir), the ALU, and the connections among these components. The numbers adjacent to the diagonal slashes on the connections indicate the number of separate connections that are represented by the corresponding lines. Registers %r0 – %r31 are directly accessible by a user. Register %r0 always con- tains the value 0, and cannot be changed. The %pc register is the program counter, which keeps track of the next instruction to be read from the main memory. The user does not have direct access to %pc, but can access it indirectly through the call and jmpl instructions. The temporary registers are used in interpreting the ARC instruction set, and are not visible to the user. The %ir register holds the current instruction that is being executed. The %ir register is internal to the microarchitecture and is not visible to the user. • The ALU The ALU performs one of 16 functions on the A and B busses according to the table shown in Figure 9-4. Some of the operations do not set the condition codes, which allows the control section to use the ALU without disturbing their settings. Only operations that end with “CC” affect the condition codes. CHAPTER 9 THE CONTROL UNIT 287 Mnemonic Meaning ld Load a register from memory st Store a register into memory sethi Load the 22 most significant bits of a register andcc Bitwise logical AND orcc Bitwise logical OR orncc Bitwise logical NOR srl Shift right (logical) addcc Add call Call subroutine jmpl Jump and link (return from subroutine call) be Branch if equal bneg Branch if negative bcs Branch on carry bvs Branch on overflow ba Branch always op 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SETHI Format 00 rd op2 imm22 Branch Format 000 cond op2 disp22 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CALL format 01 disp30 i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 10 rd op3 rs1 0 00000000 rs2 Arithmetic Formats 10 rd op3 rs1 1 simm13 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 11 rd op3 rs1 0 00000000 rs2 Memory Formats 11 rd op3 rs1 1 simm13 op Format op2 Inst. op3 (op=10) op3 (op=11) cond branch 00 SETHI/Branch 010 branch 010000 addcc 000000 ld 0001 be 01 CALL 100 sethi 010001 andcc 000100 st 0101 bcs 10 Arithmetic 010010 orcc 0110 bneg 11 Memory 010110 orncc 0111 bvs 100110 srl 1000 ba 111000 jmpl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PSR n zvc Figure 9-2 Instruction subset and instruction formats for the ARC. The ANDCC and AND operations perform a bit-by-bit logical AND of corre- sponding bits on the A and B busses. The ORCC and OR operations perform a bit-by-bit logical OR of corresponding bits on the A and B busses. The NORCC and NOR operations perform a bit-by-bit logical NOR of corresponding bits on the A and B busses. The ADDCC and ADD operations carry out addition using two’s complement arithmetic on the A and B busses. 288 CHAPTER 9 THE CONTROL UNIT C bus A bus B bus a 0 %r0 38 0 A Decoder 1 %r1 a3 7 6 2 %r2 3 %r3 4 %r4 C c 37 b 1 38 0 B Decoder %r5 5 Decoder c3 b3 7 %r6 6 6 7 6 %r7 7 From Control 8 %r8 Unit 9 %r9 CLOCK UNIT 10 %r10 . 30 %r30 %r31 32 31 32 %pc 64-to-32 %temp0 MUX 33 %temp1 C Bus 34 MUX 35%temp2 36%temp3 37 %ir MUX Control 32 32 24 Data To Main Line (From 32 Memory Control Unit) F0 F From 32 ALU 1 To Control F2 Control Address To F3 Unit Unit Main Memory Data From Main Memory Data From 4 n, z, v, c Set Condition Codes Figure 9-3 The datapath of an example ARC implementation. The SRL (shift right logical) operation shifts the contents of the A bus to the right by the amount specified on the B bus (from 0 to 31 bits). Zeros are copied CHAPTER 9 THE CONTROL UNIT 289 F3 F2 F1 F0 Operation Changes Condition Codes 0 0 0 0 ANDCC (A, B) yes 0 0 0 1 ORCC (A, B) yes 0 0 1 0 NORCC (A, B) yes 0 0 1 1 ADDCC (A, B) yes 0 1 0 0 SRL (A, B) no 0 1 0 1 AND (A, B) no 0 1 1 0 OR (A, B) no 0 1 1 1 NOR (A, B) no 1 0 0 0 ADD (A, B) no 1 0 0 1 LSHIFT2 (A) no 1 0 1 0 LSHIFT10 (A) no 1 0 1 1 SIMM13 (A) no 1 1 0 0 SEXT13 (A) no 1 1 0 1 INC (A) no 1 1 1 0 INCPC (A) no 1 1 1 1 RSHIFT5 (A) no Figure 9-4 ARC ALU operations. into the leftmost bits of the shifted result, and the rightmost bits of the result are discarded. LSHIFT2 and LSHIFT10 shift the contents of the A bus to the left by two and 10 bits, respectively. Zeros are copied into the rightmost bits. SIMM13 retrieves the least significant 13 bits of the A bus, and places zeros in the 19 most significant bits. SEXT13 performs a sign extension of the 13 least significant bits on the A bus to a 32-bit word. That is, if the leftmost bit of the 13 bit group is 1, then 1’s are copied into the 19 most significant bits of the result, otherwise, 0’s are copied into the 19 most significant bits of the result. The INC operation increments the value on the A bus by one, and the INCPC operation increments the value on the A bus by four, which is used in incrementing the PC register by one word (four bytes). INCPC can be used on any register placed on the A bus. The RSHIFT5 operation shifts the operand on the A bus to the right by 5 bits. When applied three times in succession to a 32-bit instruction, this operation has the effect of placing the leftmost bit of the COND field in the Branch format (refer to Figure 9-2) into the position of bit 13. This operation is used in decod- ing the Branch instructions. For every ALU operation, the 32-bit result is placed on the C bus, unless it is blocked by the C bus MUX when a word of memory is placed onto the C bus instead. 290 CHAPTER 9 THE CONTROL UNIT Every arithmetic and logic operation can be implemented with just these ALU operations. For instance, a subtraction can be implemented by forming the two’s complement negative of the subtrahend (making use of the NOR operation and adding 1 to it) and then performing addition on the operands. A shift to the left by one bit can be performed by adding a number to itself. A “do-nothing” opera- tion, which is frequently needed for simply passing data through the ALU with- out changing it, can be implemented by logically ANDing an operand with itself and discarding the result in %r0.