Intel FPGA Programmable Acceleration Card N3000 Data Sheet Updated for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs: 1.1 Subscribe DS-1062 | 2021.06.30 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction .................................................................................................................. 3 2. Overview........................................................................................................................ 5 2.1. Intel FPGA PAC N3000 Block Diagram.......................................................................5 2.2. Overview of Product Features.................................................................................. 7 2.2.1. Intel Arria 10 GT FPGA .............................................................................. 7 2.2.2. Intel Ethernet Controller XL710-BM2 Network Interface Controller....................7 2.2.3. On-Board Memory .................................................................................... 8 2.2.4. Software and Firmware ..............................................................................8 2.2.5. Power ..................................................................................................... 9 2.2.6. Network Interface ................................................................................... 10 2.3. PCIe Overview ....................................................................................................11 2.4. Board Management Controller Overview .................................................................12 2.4.1. Field Replaceable Unit Identification (FRUID) EEPROM...................................13 3. System Compatibility ................................................................................................... 15 4. Mechanical Information ............................................................................................... 16 5. Thermal Specifications ................................................................................................. 19 5.1. Cooling Requirements ..........................................................................................21 6. Intel Provided FPGA Image ..........................................................................................23 A. References....................................................................................................................24 B. Safety and Regulatory Information...............................................................................25 B.1. Regulatory Compliance......................................................................................... 25 C. Document Revision History for Intel FPGA Programmable Acceleration Card N3000 Data Sheet....................................................................................................31 Intel FPGA Programmable Acceleration Card N3000 Data Sheet Send Feedback 2 DS-1062 | 2021.06.30 Send Feedback 1. Introduction Figure 1. Intel FPGA Programmable Acceleration Card N3000 This data sheet describes the Intel FPGA Programmable Acceleration Card N3000, featuring the Intel® Arria® 10 GT FPGA. This document provides electrical, mechanical, thermal, and other key specifications. This data sheet assists network operators and system integrators to properly deploy this Intel FPGA PAC into their servers. It also documents the FPGA power envelope, connectivity speeds to memory, and network connectivity, so that accelerator function unit (AFU) developers can properly design and test their IP. The Intel FPGA PAC N3000 is supported by the Intel Acceleration Stack for Intel Xeon® CPU with FPGAs. The Intel Acceleration Stack provides a common developer interface to both application and acceleration function developers and includes drivers, Application Programming Interfaces (APIs) and an FPGA factory image. For information about using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, refer to the Intel Acceleration Stack User Guide for Intel FPGA Programmable Acceleration Card N3000. Note: Contact your Intel field sales representative for documentation for the Intel FPGA PAC N3000. Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015 application or use of any information, product, or service described herein except as expressly agreed to in Registered writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Introduction DS-1062 | 2021.06.30 Intel validates each Intel FPGA PAC N3000 to support large scale deployments requiring FPGA acceleration. This platform is targeted for market-specific acceleration in applications such as: • Network Function Virtualization (NFV) • Multi-Access Edge Computing (MEC) • Video Transcoding • Cyber Security • High-Performance Computing • Finance Related Information Intel Acceleration Stack User Guide for Intel FPGA Programmable Acceleration Card N3000 Intel FPGA Programmable Acceleration Card N3000 Data Sheet Send Feedback 4 DS-1062 | 2021.06.30 Send Feedback 2. Overview This chapter provides an overview of the programmable acceleration card and describes the board architecture and its components. 2.1. Intel FPGA PAC N3000 Block Diagram Figure 2. Intel FPGA PAC N3000 Functional Components Intel FPGA Programmable Acceleration Card N3000 QSFP28A QSFP28B 4 x 10G / 4 x 25G / 2 x 25G 4 x 10G / 2 x 25G MAC ROM EEPROM Intel C827 Intel C827 EEPROM Retimer A Retimer B NIOS Flash 4 x 10G / 4 x 25G / 2 x 25G 4 x 10G / 2 x 25G Intel MAX 10 SMBus QSA QSB Flash QDR-IV 18+18 SPI 18+18 4 x 10G/ XL2A 1 x 40G XLA Intel DDR4 16 1 x 40G 1x16 XL2B XLB XL710 #2 Intel BP 2 x 40G NIC Arria 10 FPGA Flash 4 x 10G NIC PCIe x8 DDR4 1150GT 4x16 32+32 4 x 10G/ 1 x 40G PingPong XLA XLA Intel XLB 1 x 40G XLB XL710 #1 DDR4 32+32 BP 2 x 40G NIC 4x16 PingPong Flash 4 x 10G NIC 0-7 2 x PCIe x 8 8-15 PCIe x8 PCIe Gen3 x8 PEX87 47 PCIe Switch PCIe Gen3 x8 PCIe x16 Edge Connector The Intel FPGA PAC N3000 supports the following network configurations: Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015 application or use of any information, product, or service described herein except as expressly agreed to in Registered writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 2. Overview DS-1062 | 2021.06.30 Network QSFP28 A QSFP28 B Intel XL710 #1 Intel XL710 #2 Configuration 8 x 10GbE 4 x 10GbE 4 x 10GbE 4 x 10GbE 4 x 10GbE 2 x 2 x 25GbE 2 x 25GbE 2 x 25GbE 2 x 40GbE 2 x 40GbE 4 x 25GbE 4 x 25GbE Not Used 2 x 40GbE 2 x 40GbE Intel FPGA Programmable Acceleration Card N3000 Data Sheet Send Feedback 6 2. Overview DS-1062 | 2021.06.30 2.2. Overview of Product Features 2.2.1. Intel Arria 10 GT FPGA The Intel Arria 10 FPGAs feature industry-leading programmable logic built on 20 nm process technology that integrates a rich feature set of embedded peripherals, embedded high-speed transceivers, hard memory controllers and IP protocol controllers. Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point (IEEE 754-compliant) arithmetic blocks enable the Intel Arria 10 FPGAs to deliver floating point performance of up to 1.5 TFLOPS. Intel Arria 10 FPGAs have a comprehensive set of power-saving features. Combined, these features allow developers to build a versatile set of acceleration solutions. Table 1. Intel Arria 10 GT FPGA Device Logic Adaptive Registers M20K M20K MLAB 18 x 19 Elements Logic Memory Memory Memory Multipliers (LE) Modules Blocks (Mb) (Mb) (ALMs) GT 1150 1,150K 427,200 1,708K 2713 53 12.7 3036 When developing the accelerator function for the Intel FPGA PAC N3000, select the 10AT115S1F45E1SG device. Related Information • Intel FPGA Devices Detailed information about features of the Intel Arria 10 FPGA family • Intel Arria 10 Device Data Sheet This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel Arria 10 devices. • Intel Arria 10 Device Overview This device overview provides information about known device issues affecting Intel Arria 10 GX/GT devices. It also offers design recommendations you should follow when using Intel Arria 10 GX/GT devices. 2.2.2. Intel Ethernet Controller XL710-BM2 Network Interface Controller The Intel Ethernet Controller XL710-BM2 network interface controller (NIC) provides a hardware compatible interface with Linux drivers for networking