IOP Conference Series: Materials Science and Engineering OPEN ACCESS Related content - A potent approach for the development of Embedded System Implementation on FPGA FPGA based DAQ system for HEP experiments Shuaib Ahmad Khan, Jubin Mitra, Erno System With μCLinux OS David et al. - Development of an Image Fringe Zero To cite this article: Ahmad Fairuz Muhd Amin et al 2011 IOP Conf. Ser.: Mater. Sci. Eng. 17 012049 Selection System for Structuring Elements with Stereo Vision Disparity Measurements Josef E Grindley, Andrew J Tickle and Lin Jiang View the article online for updates and enhancements. - Design and evaluation of a high- performance charge coupled device camera for astronomical imaging Yuanyuan Shang, Jie Zhang, Yong Guan et al. This content was downloaded from IP address 170.106.34.90 on 26/09/2021 at 02:27 CAMAN IOP Publishing IOP Conf. Series: Materials Science and Engineering 17 (2011) 012049 doi:10.1088/1757-899X/17/1/012049 Embedded System Implementation on FPGA System With µCLinux OS 1Ahmad Fairuz Muhd Amin , 2Ishak Aris , 3Raja Syamsul Azmir Raja Abdullah and 3Ratna Kalos Zakiah Sahbudin 1Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor, Malaysia. Email: [email protected] 2Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor, Malaysia. Email: [email protected] 3Department of Computer and Communication Systems Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor, Malaysia. Email: [email protected] Abstract Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32- bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated 1. Introduction Many embedded system designs have been implemented in a variety of applications such as mobile phones, automotive, aircraft and others electronic gadgets. These embedded system can be grouped together and communicate over a network either using wired or wireless systems. The processor used in this embedded system is based on a Softcore processor which is implemented in FPGA [1, 2]. The two major FPGA manufacturers provide commercial softcore processors namely, Xilinx offers its MicroBlaze processor [3] while Altera Nios II processor [7]. The softcore processor can be adapted and enhanced to the requirement. Many components can be added or removed without any problem such as I2C, UART, Ethernet and USB. The FPGA will be reconfigured with the new softcore processor which increases the flexibility and easy to maintain. A softcore processor is a microprocessor fully described in software, usually in hardware description language (HDL), which can be synthesized in programmable hardware, such as FPGA. Published under licence by IOP Publishing Ltd 1 2 CAMAN IOP Publishing IOP Conf. Series: Materials Science and Engineering 17 (2011) 012049 doi:10.1088/1757-899X/17/1/012049 In this paper, DE2 Education and Development Board which developed by Terasic Technologies [4] was used. This board has Cyclone II EP2C35F672C6 FPGA, 8MB SDRAM, 512KB RAM and 1MB Flash and its sufficiently powerful to support general-purpose operating system. The Ethernet is used for the communication and a web server is implemented on the embedded system. This paper deals with the implementation of µCLinux OS to the Embedded System on FPGA board to monitor the status of the peripherals input or output of the board system over a network. This embedded system is connected to the network using Ethernet interface which available on the board and setup a web server as shown in Figure 1. DE2 Board Internet With Nios II Processor Figure 1. Altera DE2 board run as a web server 2. System Architecture There are three layers in this embedded system and the development environment is as follows: 1. Bottom layer: FPGA system hardware, e.g. Altera DE2 board. 2. Middle layer: µCLinux OS 3. Top layer : User space i.e. applications program 2.1Hardware The components that need to be designed for the embedded system are as follows: - FPGA - RAM, ROM - Serial Interface - LCD, LED (for output) - Switches, buttons (for input) - Ethernet Interface The main component of the board is the FPGA which is the core of the system and always can be configured with a new softcore processor. The remaining components are SDRAMS which connected to the FPGA and its functionality as data storage. The embedded system development board is shown in Figure 2. Figure 2. Hardware Platform of Embedded System 2 3 CAMAN IOP Publishing IOP Conf. Series: Materials Science and Engineering 17 (2011) 012049 doi:10.1088/1757-899X/17/1/012049 2.2 Softcore Processor Core processor used for the system is a softcore processor and described by a hardware description language and are configure on a FPGA. Hardware description language (HDL) used is VHDL or Verilog [5] as hardware code program and configuration. This paper describes the development of an embedded system with FPGA. It is not shown how to develop softcore processor and only use the finished open source IP cores. An open source code softcore processor is free available under the General Public License(GPL). GPL license [6] can be downloaded from opencores [17]. The Tool chain, a collection of programs used for compiling and linking, exists for the development of the software as well as using of µCLinux for the processor. The advantage of this IP core is that the source code is available for free and it is very easy to change and use it. In this embedded system, a softcore processor used is Nios II and is designed by the Quartus II and Nios II IDE for hardware and software development respectively. The advantage of the NIOS II is that it is possible to develop very fast an own softcore processor and can be integrated with IP cores that provided by Quartus II. Moreover, this softcore processor is ready to use toolchain for the development of software as well as compiling µCLinux. 2.3 NIOS II Nios II is a microcontroller that is used in FPGA and was developed by Altera Corp. This microcontroller was not exists as a physical hardware, but it is available only as in the hardware description language such as in Verilog and it is called Softcore Processor. This microcontroller is without Management Memory Unit (MMU) which allows to build a lot of a different microcontroller systems such as UART, SDRAM controller, DMA interface, Ethernet interface, parallel input output (PIO) devices. As a general purpose RISC processor, the NIOS II comes with a full 32-bit instruction set, data path, address space, 32 general-purpose registers and 32 external interrupts. A NIOS II processor is equivalent to a microcontroller or “computer on a chip” that includes a processor and a combination of peripherals and memory on a single chip. The components of this such microcontroller are interconnected via the proprietary “Avalon-MM-Bus” [7] of Altera. The Avalon interface can be used to describe peripheral interface, such as SDRAM, that supports only simple, fixed cycle read/write transfers. On the other hand, Avalon-MM interface can also be used to describe a more complex pipelined interface capable of burst transfers. Figure 2 shows an example of a NIOS II system. Figure 2. A NIOS II System on FPGA 3 4 CAMAN IOP Publishing IOP Conf. Series: Materials Science and Engineering 17 (2011) 012049 doi:10.1088/1757-899X/17/1/012049 2.4 SOPC Application The traditional design modalities are ASIC and fixed-processor design. SOPC [8, 9] design has advantages and disadvantages to both of these alternatives as show in Table 1. Table 1. Comparison of SOPC, ASIC and Fixed Processor Design Modalities [11] Fixed- Feature SOPC ASIC Processor Software Flexibility Hardware Flexibility Reconfigurability Development Time/Cost Peripheral equipment cost Performance Production cost Power efficiency The strengths of SOPC design are reconfigurable, flexible nature and short development cycle. However, the disadvantages include lower maximum performance, higher unit costs in production and relatively high power consumption [10]. In Figure 2, the system contains PIOs which connected to the input e.g. switches and output e.g. LEDs and LCD. These PIOs are implemented using QUARTUS II and Nios II IDE for hardware and software development tools respectively as well as the FPGA component Cyclone II 2C35 using DE2 Development Board [4] is selected. The following IP cores are attached to this project under SOPC builder: • NIOS II (softcore processor) • Avalon MMU for bus • SRAM 512 KB (peripheral) • SDRAM 8 MB (peripheral) • Flash controller (peripheral) • Ethernet MAC controller (peripheral) • UART controller (peripheral) All the peripherals above are connected over the Avalon buses at the processor and each of peripheral, address are assigned in order to access it via the software. Nios II IDE offers a function to write an application. 4 5 CAMAN IOP Publishing IOP Conf. Series: Materials Science and Engineering 17 (2011) 012049 doi:10.1088/1757-899X/17/1/012049 The design of the hardware in Quartus II and SOPC builder is shown in Figure 3. Figure 3.Design of Hardware of FPGA The Ethernet and the serial port are used to allow communication between the softcore and external interfaces.