About the Author Dr. Steven H. Voldman received his B.S. in Eng. Science from the Univ. of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Eng. Physics (1986) and Ph.D EE (1991) from the Univ. of Vermont under IBM’s Resident Study Fellow program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability/device engineer, his work included pioneering work in bipolar/CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he was responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET scaling, device simulation, Copper, low-k, MR heads, CMOS, SOI, SiGe and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996–2000), ESD Association Technical Program Chair (2000), Vice Chairman (2001), General Chairman 2002, and ESDA Board of Directors (1998–2004), International Reliability Physics (IRPS) ESD/Latchup Sub-Committee Chairman (2002–2004), International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chair- man (2003–2005), ESD Association Standard Development Chairman on Transmission Line Pulse Testing (2000–2004), ESD International Committee on Education (ICE) Asian Uni- versity Liason and ‘‘ESD on Campus’’ university lecture program founder, and serves on the Electrical Overstress/Electrostatic Discharge (EOS/ESD), Taiwan ESD Conference (T-ESDC), Bipolar Circuit Technology Meeting (BCTM), and the International Conference on Electro- magnetic Compatibility (ICEMAC, Taipei, Taiwan) technical program committees. Voldman has provided ESD lectures for universities and institutions in the United States, Singapore, Malaysia, Taiwan and China. He is a recipient of over 144 US patents, over 125 publications, and recently wrote a first textbook on ESD entitled ESD: Physics and Devices, a third textbook ESD:RF Technology and Circuits, as well as a contributor to the text Silicon Germanium: Modeling, Technology and Simulation. Voldman also provides talks on patenting, and invention to corporations and inventors. He has been highlighted in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the Oct. 2002 edition of Scientific American entitled ‘‘Lightning Rods for Nanoelectronics,’’ and Pour La Science, Le Scienze, and Swiat Nauk international editions. In 2003, Dr. Voldman was accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ‘‘contributions to electrostatic discharge protection in CMOS, SOI and SiGe technologies.’’ Acknowledgments I would like to thank the individuals who have helped me in my academic and professional career path. The academic foundation gave me the ability to cross from physics to circuits and to address the field of electrostatic discharge (ESD) in ESD protection circuitry. Faculty from the University of Buffalo, Massachusetts Institute of Technology, and University of Vermont had significant impact on my direction and interest in the area of continuum mechanics, continuum electro-mechanics, electrostatics, semiconductors, field theory, sys- tems, and circuits as well as mathematics and physics. I am indebted to the Engineering Science, Physics Department, and Electrical Engineering curriculums at the University of Buffalo for support and interest in the thermal, mechanical, and electrical sciences; faculty includes Professor Irving Shames, Professor Herbert Reismann, Professor Stephen Margolis, Professor J. J. Whalen, Professor R. K. Kaul, Professor Reichert, and others. At Massachusetts Institute of Technology, I am indebted to the Electrical Engineering (EE) Department, Nuclear Engineering Department, the Physics Department, M.I.T. Plasma Fusion Center, and M.I.T. High-Voltage Research Laboratory (HVRL) for the support in the area of plasma physics, electrodynamics, electrostatics, and semiconductors. The faculty of Professor James R. Melcher, Professor Markus Zahn, Professor Cliff Fonstad, Professor Louis D. Smullin, Professor J. A. Kong, Professor David Epstein, and Professor C. Cook as well as other EE faculty contributed to my understanding of the continuum electro-mechanics, electrostatics, and semiconductors in the area of technical material, course material development, education, and educational texts. As an M.I.T. graduate student teaching assistant, I was fortunate to be able to observe and participate in the teaching of semiconductor devices and circuits under the undergraduate semiconductor course 6.012 with Professor Cliff Fonstad, Professor David Epstein, Professor Wyatt, and Professor Hank Smith. At the University of Vermont, I was able to continue many additional courses in the area of semiconductors, circuits, microprocessors, and system theory under faculty members of R. L. Anderson and S. Titcomb. This allowed me to continue to grow in the area of semiconductor physics, integrated circuit technology, and circuits. At IBM, I was fortunate to have many mentors and friends from IBM Burlington Vermont, IBM East Fishkill, IBM T. J. Watson Research Center, as well as circuit designers from IBM Poughkeepsie, IBM Rochester, IBM Austin, IBM FSD Manassas, Kingston, IBM Endicott, IBM Raleigh, IBM Boeblingen, IBM Singelfingen, and IBM Essonnes. For this text, the ESD learning came from collaborating and working with IBM circuit teams, ESD test laboratory, and failure analysis engineers from Bipolar SRAMs, CMOS DRAMs, CMOS xxvi ACKNOWLEDGMENTS SRAMs, bulk CMOS and SOI microprocessors, ASIC development, and today in the field of mixed signal RF CMOS and RF BiCMOS Silicon Germanium semiconductor chips. The ESD circuit learning was driven by the creative interaction of one semiconductor device engineer and a very large global circuit design community whose products became the opportunity to demonstrate ESD success or ESD failure. I would like to thank the circuit designers, I/O teams, ESD test laboratory, and failure analysis engineers where together we learned the interaction and issues of ESD in semiconductor chips—Roy Flaker (bipolar and CMOS SRAM), Jack Gersbach (bipolar SRAM), Russel Houghton (SRAM), Jeffery Chu (SRAM), Richard Parent (4Mb-DRAM), Howard Kalter (16-Mb DRAM), H. S. Lee (CMOS SRAM), David Pricer, Thomas Maffit (16-Mb DRAM), Jeffery Dreibelbis (16-Mb DRAM), Charles Drake (16-Mb DRAM), David Hui (CMOS Server Division I/O), Daniel Dreps (CMOS ASIC, and CPU), Robert Williams (CMOS AS-400 CPU), Daniel Young (CMOS AS-400 CPU), John Bialas (PowerPC 601þ), Roger Gregor (CMOS ASICs), Harold Pilo (CMOS SRAM), Geordie Braceras (CMOS SRAM), John Connors (CMOS SRAM), Tony Correale (PowerPC Embedded Controllers), Douglas Stout (ASIC I/O), Ron Piro (ASIC I/O), Jeffery Sloan (ASIC), James Pequignot (ASIC), Francis Chan (ASIC), Sam Ray (Disk Drive), Stephen Ames (Optical Interconnect), Lloyd Walls (Austin CPU), Anthony Bonnaccio (Bipolar Specials), and others. Outside of IBM, I am indebted to circuit designers and the microprocessors teams whom I had an opportunity to work with: Motorola/IBM PowerPC 602, 603, 604, 620, 640 teams (lead: Gianfranco Gerosa), AMD K6 team (lead: Don Draper and Stephen Beebe), the Digital Alpha team (lead: Larry Baer), the Compaq Alpha team (lead: Warren Anderson), NEXGEN x386 and x486 teams (lead: Don Draper), the TRANSMETA Scorpion, and Tarantula microprocessor teams (lead: Mark Johnson), IDT microprocessors, Sun microprocessors (lead: Avi Leibenmensch), and the Cyrix x86 teams in development of floor planning, circuits, and ESD devices. In the ESD laboratory, I would like to thank Vaughn Gross, Christine Blakemore, Rebecca Ryan, Josee Coutinho, Matt Hausmann, Ernie Goodrich, and Richard Serafin for HBM, MM, and TLP testing support. For years of ESD test site and design support, I would like to thank Joann Howard of IBM. I would like to thank the IBM failure analysis team for years of diagnosing ESD failures to assist in the ESD learning process on SEM, TEM, EMMI, AFM, and PICA tools: James Never, Peter Czahor, Ted Regula, Jim Pecozzi, David Vallet, Ted Levin, Phil Kaszuba, Dick Ross, and all the others. In the semiconductor development, I would also like to thank peers and co-workers in the Bipolar, CMOS, and Silicon Germanium teams: Michael Hargrove, James Slinkman, Stephen Furkay, Jeffery B. Johnson, Stephen Geissler, Toshi Furukawa, Jim Nakos, Jim Adkisson, Terry Hook, and Chris Long. I would like to thank my managers Richard Ross, John Hiltebeitel, Jim McNichol, Mark Hakey, Jim Dunn, and Stephen St. Onge in the support of my ESD and latchup work. I was fortunate for the last 23 years to have the advice and counsel of many IBM engineers and scientists. I was very fortunate to interact and have as semiconductor mentors and guidance from my first years at IBM: Ron Troutman, Wendell Noble, Badih El-Kareh, Ed Nowak, Eric Adler, George Sai-Halasz, Tak Ning, Denny Tang, Robert Dennard, Matt Wordeman, Jack Y.-C. Sun, John Aitkens, Paul Bakeman, Andre LeBlanc, Andre Forcier, Bruno Aimi, Charles Stapper, and Peter Cottrell. For publication support, I would like to thank Dorie Gentes of IBM Technical Communications for 20 years of publication editing and support. Additionally, I would like to thank the IBM Burlington patent legal team for years of support and teaching about ESD patents. ACKNOWLEDGMENTS xxvii In the ESD discipline,