Memory Solid-State Memory Chips SRAM, DRAM PENN J. Van der Spiegel EE200- 1 Simple Processor Datapath Consists of Registers, Combinational Logic and Buses Address Bus Result Bus Memory ALU A Memory Address M P I A M Data Bus Bus A C R C B R R B MEMORY Memory Bus Memory Address Register (MAR) Main Memory: Instruction Register (PR) Accumulator or Data Register (AC) SRAM; DRAM Memory Buffer Register (MBR) Program Counter (PC) PENN EE200- 2 J. Van der Spiegel (Katz, Contemporary Logic Design) Memory in a Computer PENN J. Van der Spiegel EE200- 3 Memory Hierarchy Fast Registers Pro- cessors 1st Level SRAM Speed Cache Cost 2nd Level SRAM - Increase Cache DRAM Increase Main Memory DRAM Magnetic Archive I Disk/Tape Archive II Optical Disk PENN J. Van der Spiegel EE200- 4 Memory capacity and Moore’s Law Memory capacity has increased about 1.5x/yr Memory technology is more aggressive than for microprocessors: Technology Driver 10 10 1GDRAM 1G Giga chip DRAMs Microprocessors 256 M 8 64 M P7 10 16 M 10M 1 MDRAM P6 MPU only 6 Mega chip 256 K Pentium 10 1M 64 K 486 100K 16 K 68020 Power PC 1K DRAM 68000 601 4 10K 10 8080 32-bit 1K 4004 Micro 2 8-bit 16-bit 10 100 invention Micro Micro 10 of the IC 0 Transistors per chip 1 10 PENN 1960 1970 1980 1990 2000 J. Van der Spiegel EE200- 5 Memory types 1. Non-volatile Memory: » Is a memory which keeps its data even when power is switched off. All other memories are volatile. 2. Volatile Memories 2.1 Dynamic Memory (DRAM): » Is a volatile memory where information is stored on a capacitor. Refreshing needed. 2.2 Static Memory (SRAM): » Is a volatile memory where information is maintained as long as the power is switched on. Internal feedback makes the memory static (latch). PENN J. Van der Spiegel EE200- 6 Memory types - overview MEMORIES VOLATILE NON-VOLATILE Read-only memory ROM SRAM DRAM Programmable Read-onlyr memory Static Dynamic PROM Random Access EDO SDRAM Erasable PROM DDSRAM EPROM RAMBus Electrically erasable PROM EEPROM Non-volatileRAM EDO: Enhanced Data Out DRAM NVRAM SDRAM: Synchronous DRAM Battery-backup RAM DDSRAM: double data rate synch. DRAM (266MHz) BRAM FerroelectricRAM NVRAM: - Combination of SRAM and EEPROM; FERRAM MRAM: - Magnetoresistive RAM Ferromagnetic PENN MRAM J. Van der Spiegel EE200- 7 DRAM Memory Technology Word line Poly 6 common capacitor plate + + Poly 4 individual -- capacitor plate Bitline Polycide 3 bit line Samsung 64 Mbit DRAM(Source: ICE Corp.) PENN J. Van der Spiegel EE200- 8 DRAM cell Word line Bit-line Capacitor Transistor (switch) IBM 256 Mb DRAM; Sc. Am. Jan. 02) PENN J. Van der Spiegel EE200- 9 DRAM: System Architecture Writing a bit=1 at Word 0, bit position 5 (Source: Intel Museum www.intel.com/intel/intelis/museum/exhibit/memory_tech/ PENN J. Van der Spiegel EE200- 10 DRAM: System Architecture Random Access Memory Row Decoder 1 1 MATRIX OF MEMORY Row address CELLS one cell N N 2 1 2 M Read Column decoder Write Control 1 M l Out In Data Column address Storage capacity: ( 2 N ) ( 2 M ) = 2 N+M bits PENN J. Van der Spiegel EE200- 11 Giga-bit DRAM NOTE: One 4G DRAM stores the complete works of Shakespeare 64 times! or 47 min. of full-motion video) 64 Gbit DRAM expected in 2016!!! PENN J. Van der Spiegel EE200- 12.