Intel® Itanium® Architecture Software Developer’s Manual Volume 3: Intel® Itanium® Instruction Set Reference Revision 2.3 May 2010 Document Number: 323207 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. 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Intel® Itanium® Architecture Software Developer’s Manual, Rev. 2.3 644 Contents 1 About this Manual . 3:1 1.1 Overview of Volume 1: Application Architecture . 3:1 1.1.1 Part 1: Application Architecture Guide . 3:1 1.1.2 Part 2: Optimization Guide for the Intel® Itanium® Architecture . 3:1 1.2 Overview of Volume 2: System Architecture. 3:2 1.2.1 Part 1: System Architecture Guide . 3:2 1.2.2 Part 2: System Programmer’s Guide . 3:3 1.2.3 Appendices. 3:4 1.3 Overview of Volume 3: Intel® Itanium® Instruction Set Reference . 3:4 1.4 Overview of Volume 4: IA-32 Instruction Set Reference. 3:4 1.5 Terminology . 3:5 1.6 Related Documents . 3:5 1.7 Revision History . 3:6 2 Instruction Reference . 3:11 2.1 Instruction Page Conventions. 3:11 2.2 Instruction Descriptions . 3:13 3 Pseudo-Code Functions . 3:281 4 Instruction Formats . 3:293 4.1 Format Summary . 3:294 4.2 A-Unit Instruction Encodings . 3:300 4.2.1 Integer ALU . 3:300 4.2.2 Integer Compare. 3:302 4.2.3 Multimedia . 3:306 4.3 I-Unit Instruction Encodings . 3:310 4.3.1 Multimedia and Variable Shifts . 3:310 4.3.2 Integer Shifts . 3:315 4.3.3 Test Bit . 3:316 4.3.4 Miscellaneous I-Unit Instructions . 3:318 4.3.5 GR/BR Moves. 3:320 4.3.6 GR/Predicate/IP Moves . 3:321 4.3.7 GR/AR Moves (I-Unit). 3:321 4.3.8 Sign/Zero Extend/Compute Zero Index . 3:322 4.3.9 Test Feature . 3:323 4.4 M-Unit Instruction Encodings . 3:323 4.4.1 Loads and Stores . 3:323 4.4.2 Line Prefetch . 3:337 4.4.3 Semaphores . 3:338 4.4.4 Set/Get FR . 3:339 4.4.5 Speculation and Advanced Load Checks. 3:340 4.4.6 Cache/Synchronization/RSE/ALAT . 3:341 4.4.7 GR/AR Moves (M-Unit). 3:342 4.4.8 GR/CR Moves . 3:343 4.4.9 Miscellaneous M-Unit Instructions . 3:344 4.4.10 System/Memory Management . 3:345 4.4.11 Nop/Hint (M-Unit) . 3:349 4.5 B-Unit Instruction Encodings . 3:349 4.5.1 Branches . 3:350 4.5.2 Branch Predict/Nop/Hint . 3:353 4.5.3 Miscellaneous B-Unit Instructions . 3:355 4.6 F-Unit Instruction Encodings. 3:356 4.6.1 Arithmetic . 3:358 Intel® Itanium® Architecture Software Developer’s Manual, Rev. 2.3 645 4.6.2 Parallel Floating-point Select. 3:359 4.6.3 Compare and Classify . 3:359 4.6.4 Approximation . 3:361 4.6.5 Minimum/Maximum and Parallel Compare . 3:362 4.6.6 Merge and Logical. 3:363 4.6.7 Conversion . 3:363 4.6.8 Status Field Manipulation . 3:364 4.6.9 Miscellaneous F-Unit Instructions . 3:365 4.7 X-Unit Instruction Encodings . 3:365 4.7.1 Miscellaneous X-Unit Instructions . 3:365 4.7.2 Move Long Immediate64 . 3:366 4.7.3 Long Branches . 3:367 4.7.4 Nop/Hint (X-Unit) . 3:368 4.8 Immediate Formation. 3:368 5 Resource and Dependency Semantics . 3:371 5.1 Reading and Writing Resources . 3:371 5.2 Dependencies and Serialization . 3:371 5.3 Resource and Dependency Table Format Notes . 3:372 5.3.1 Special Case Instruction Rules . 3:374 5.3.2 RAW Dependency Table. 3:374 5.3.3 WAW Dependency Table . 3:383 5.3.4 WAR Dependency Table. 3:387 5.3.5 Listing of Rules Referenced in Dependency Tables . 3:387 5.4 Support Tables . ..