Computer Systems Structure Input/Output Peripherals Computer Central Main Processing Memory Unit Computer Systems Interconnection Input Output Communication lines CS 160 Ward 1 CS 160 Ward 2 Examples of I/O Devices • Human readable (Communicating with user) – Screen, printer, keyboard, etc. Basic I/O Concepts & • Machine readable (Communicating with Terminology equipment) – Magnetic disk, tape systems, etc. – Cameras, audio speakers, etc. – Sensors, actuators, etc. • Communication (Communicating with remote devices) – Modems, Network Interface Card (NIC), etc. CS 160 Ward 3 CS 160 Ward 4 Illustration of Early Devices Input/Output Problems • Wide variety of peripherals – Delivering different amounts of data – At different speeds – In different formats • All slower than CPU and RAM • Independent of processor – Separate circuitry & power • Connected by digitals signals CS 160 Ward 5 CS 160 Ward 6 Typical I/O Data Rates (~Year 2000) Input/Output Problems • Wide variety of peripherals – Delivering different amounts of data – At different speeds – In different formats • All slower than CPU and RAM Need I/O controllers with interfaces to effectively handle. CS 160 Ward 7 CS 160 Ward 8 Illustration of Modern Interface Controller I/O Controller Functions • Control & Timing • CPU Communication • Device Communication • Data Buffering • Error Detection • Needed at each end of a physical connection • Allows arbitrary voltage and signal on connection CS 160 Ward 9 CS 160 Ward 10 I/O Controller Illustration Two Types of Interfaces • Parallel interface – Composed of many wires – Each wire carries one bit at any time – Width is number of wires • Serial interface – Single signal wire (also need a ground) – Bits sent one-at-a-time – Slower than parallel interface CS 160 Ward 11 CS 160 Ward 12 Clock(s) Duplex Technology • Ends of connection typically use • Full-duplex separate clocks, and controllers manage – Simultaneous, bi-directional transfer differences – Example: disk drive supports simultaneous read and write • Transmission is self-clocking if signal • Half-duplex encoded in such a way that receiving – Transfer in only one direction at a time controller can determine boundary of – Interfaces must negotiate access before bits transmitting CS 160 Ward 13 CS 160 Ward 14 Latency and Throughput Data Multiplexing • Fundamental idea • The latency of an interface is a measure • Arises from hardware limits on parallelism of the time required to perform a single (pins or wires) bit transfer • Allows sharing of hardware • The throughput of an interface is a • Multiplexor – Accepts input from many sources measure of the data that can be – Sends small amount from one source before transferred per unit time accepting another • Demultiplexor – Receives transmission of pieces – Sends each piece to appropriate destination CS 160 Ward 15 CS 160 Ward 16 Illustration of Mutiplexing Multiplexing and I/O Interfaces • Multiplexing is used to construct an I/O interface that can transfer arbitrary amounts of data over a fixed number of parallel wires • Multiplexing hardware divides the data into blocks, and transfers each block independently • 64 bits of data multiplexed over 16-bit path CS 160 Ward 17 CS 160 Ward 18 Multiple Devices per External Interface Processor View of I/O • Cannot afford separate interface per • Processor does not access external device devices directly – Too many wires • Instead, processor uses a programming interface to pass requests to an – Not enough pins on processor chip interface controller • Example • Programming interface translates the – I/O devices, memory, etc. sharing a requests into the appropriate external common bus. signals CS 160 Ward 19 CS 160 Ward 20 Definition of a Bus • Digital interconnection mechanism • Allows two or more functional units to transfer data Buses & Bus Architectures • Typical use: connect processor to – Memory – I/O Devices • Design can be – Proprietary (owned by one company) – Standardized (available to many companies) CS 160 Ward 21 CS 160 Ward 22 Illustration of a Bus Sharing • Most buses are shared by multiple devices • Need an access protocol – Determines which device can use the bus at any time – All attached devices must follow the protocol • Note: can have multiple buses in one computer CS 160 Ward 23 CS 160 Ward 24 Characteristics of a Bus Physical Bus Connections • Parallel data transfer • Several possibilities – Can transfer multiple bits at the same time – Wires on a circuit board or chip – Typical width is 32 or 64 bits – Sockets on boards • Passive – Bus does not contain many electronic components – Combinations – Attached devices handle communication • Conceptual view: think of a bus as parallel wires • Bus may have arbiter that handles sharing CS 160 Ward 25 CS 160 Ward 26 Illustration of Bus on a Motherboard Illustration of Circuit Board and Corresponding Sockets CS 160 Ward 27 CS 160 Ward 28 Bus Interface Conceptual Design of a Bus • Nontrivial • Need three functions • Controller circuit required – Control – Address specification – Data being transferred • Conceptually three separate groups of wires (lines) CS 160 Ward 29 CS 160 Ward 30 Illustration of Lines in a Bus Bus Access • Bus only supports two operations – fetch (also called read) – store (also called write) • Access paradigm known as fetch-store paradigm • Obvious for memory access • Surprise: all operations, including I/O, must be performed using fetch-store paradigm CS 160 Ward 31 CS 160 Ward 32 Fetch-Store Over a Bus Width of a Bus • Fetch • Larger width – Place an address on the address lines – Higher performance – Use control line to signal fetch operation – Higher cost – Wait for control line to indicate operation complete – Requires more pins • Store • Smaller width – Place an address on the address lines – Lower cost – Place data items on the data lines – Lower performance – Use control lines to signal store operation – Requires fewer pins – Wait for control line to indicate operation complete • Compromise: multiplex transfers to reduce width CS 160 Ward 33 CS 160 Ward 34 Multiplexing Illustration of Multiplexing on a Bus • Reuse lines for multiple purposes • Extreme case – Serial bus has one line • Typical case – Bus has K lines – Address and data are K bits wide • Transfer takes longer with multiplexing • Controller hardware is more sophisticated CS 160 Ward 35 CS 160 Ward 36 Effect of Bus Multiplexing on Design Illustration of Memory Bus • Addresses and data are multiplexed over a bus • To optimize performance of the hardware, an architect chooses a single size for both data items and addresses • Address over bus used to activate desired memory unit CS 160 Ward 37 CS 160 Ward 38 Control Hardware and Addresses Steps an Interface Takes • Although all interfaces receive all Let R be the range of addresses assigned to the memory requests that pass across the bus, an Repeat forever { interface only responds to requests that Monitor the bus until a request appears; contain an address for which the if (the request specifies an address in R) { interface has been configured respond to the request } else { ignore the request } } CS 160 Ward 39 CS 160 Ward 40 Potential Errors on a Bus Address Configuration and Sockets • Two options for address configuration • Address conflict – Configure each interface with the set of addresses – Two devices attempt to respond to a given – Arrange sockets so that wiring limits each address socket to a range of addresses • Unassigned address • Latter avoids misconfiguration: owner can – No device responds to a given address plug in additional boards without configuring the hardware • Note: some systems allow MMU to detect Bus hardware reports a bus error. and configure boards automatically CS 160 Ward 41 CS 160 Ward 42 Using Fetch-Store with Devices Example: Meaning Assigned to Addresses • Example Address Operation Meaning – Imaginary status light controller Nonzero data value turns the display 100-103 store on, and a zero data value turns the – Connected to 32-bit bus display off – Contains N separate lights Returns zero if display is currently off, 100-103 fetch and nonzero if display is currently on – Desired functions are Change brightness. Low-order four bits • Turn display on of the data value specify brightness 104-107 store • Turn display off value from zero (dim) through sixteen (bright) • Set display brightness Low order sixteen bits of data value • Turn status light i on or off each controls a status light, where zero 108-111 store sets the corresponding light off and one sets it on CS 160 Ward 43 CS 160 Ward 44 Example: Interpretation of Operations Unified Memory & Device Addressing • Semantics are if (address == 100 && op == store && data != 0) • Single bus can attach turn_on_display; – Multiple memories and if (address == 100 && op == store && data == 0) – Multiple devices turn_off_display; • Bus address space includes all units • Circuits actually test the address, operation, and data values in parallel and take appropriate action CS 160 Ward 45 CS 160 Ward 46 Example: Bus with Memories & Devices Example: Bus Addressing Bus Address Space Address Assignments • Two memories and two I/O devices Address space may be contiguous or may have holes CS 160 Ward 47 CS 160 Ward 48 Address Map Bridge Connecting Two Buses • Specifies types of hardware that can be used for different addresses • Part of bus specification • Example on the right – 16-bit bus – Bus can support up to 32,768 bytes • An interconnection device • In a typical computer, the part of the address space • Maps range