High Performance Embedded Software Design for Protective Relay Algorithm in Digital Signal Processors Heung Sun Yoon, Myungha Kim, Jong Kang Park, and Jong Tae Kim Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea Abstract - Most measurements and protective algorithms for - The number of channels are increased with single DSP, since power systems have been implemented by embedded software processing speed is improved. in more than a single digital signal processor (DSP). As more complex functions required for intelligent electronic devices, - Coordination accuracy is always guaranteed within the we need to improve the existing software solutions for DSPs in designated fixed-point range, since simplification is not terms of execution time, cost and reliability. This paper applied. It is easy to change parameters to handle various suggests a fixed-point design technique for several requirements. mathematical functions in relay algorithms. By porting it to a real target system, we also evaluated that the proposed design By the result of this paper, the fixed-point can give higher speed of operations, higher sample rate and implementation in TMS320C 6416 requires additional 128 more increasing concurrent channel support capability than bytes non-volatile memory compared to the software of the existing solution. floating-point version. However, the operation speed is Keywords: protective relay, digital signal processor, fixed- improved by 53 times and the entire code memory usage is point design reduced by 25%. Furthermore, our code is running 27 times faster than the DSP embedding the floating point unit. 1 Introduction 2 Fixed-point design of relay algorithm Protective relays have been used for preventing and minimizing damage by detecting electric power system faults In this section, the optimization of protective relay such as short circuit and ground fault in a timely manner. In algorithm, hardware specifications and each details of the today, key features of protective relay are supporting multi- fixed-point design will be covered. channel sources and high precision protection control. Furthermore, there is a trend that equipment monitoring and control, communication and prevention diagnosis are required. 2.1 Software of protective relay Requests of operation performance have been extremely enlarged in order to implement these demands [1,2]. The main difference between the digital and traditional Therefore, more than two processors have been used to analog protective relay is that the digital protective relay is implement the protective relay in the existing design [3,4,5]. implemented by software which is executed by the instruction set architecture. Most of digital protective relay features such In this paper, we proposed embedded software as protection, auto-monitoring, and man machine interface optimized fixed point design for digital filter and protective (MMI) are implemented by software. algorithms. We presented expected processing speed of processor which has floating-point operations contrast with The digital protective relay provides a number of processer which doesn’t have. And we verified that low-cost features. As shown in Fig. 1, the embedded software divided single DSP is possible to provide high-quality protective into three categories such as protective relay software, relaying by optimizing operations. interface and diagnosis software. Protective relay software include digital filter, protective algorithm, control sequence. Our design provide following advantages. Diagnosis software perform regular monitoring, auto- and self-diagnosis and MMI software which processes correction - Single DSP can provide high sample rate which is 128 value and display. Protective relay software is being samples/period or more in real-time by improving processing processed as a top priority, normal human machine interface speed so that we get more information from the electric power software and diagnosis software will perform in the free time. system. Fig 2 illustrates basic structure of protective relay software - High sample rate improves noise cancellation performance which is main subject of this paper. Voltage and current of digital filter, as the result high quality protective relay is signals are came from external Potential Transformer (PT), possible. Current Transformer (CT) and then these signals pass low- pass analog filter. After converting these signals by analog-to- Protective Relay S/W I/F S/W Diagnosis S/W 64KB RAM is used for level 2 program cache (L2P), 32 bits data are transferred from L2P to L1P in a clock. In case that 64KB RAM is used for data memory, 32 bits data are I/O Control, Digital Filter, Continuous Serial I/F, transferred to L1D in a clock. Measurement, Surveillance, Network I/F, Protective Algorithm, Auto- and Self- Display and Monitor Control Sequence diagnosis 2.3 Fixed-point design of digital filter High harmonic components of voltage and current signals which come from external analog circuit are Fig. 1 Embedded S/W for Protective Relay eliminated by the digital filter. And then, the protective algorithm can be applied. In general, speed and reliability of digital converter (ADC), timer interrupt service routines store digital protective relay are primarily determined by designing data in the internal memory buffer at specified period. digital filter. We used DFT (Discrete Fourier Transform) Unnecessary harmonic components are removed by digital filter for the relay. As shown in Fig. 4, Xre(k) and Xim(k) filter at each reading voltage and current samples. Essential which are real number and imaginary number of X(n) information to monitor and relay are extracted by measuring respectively are calculated to obtain k harmonic component root-mean-square (RMS) value, phase and frequency. by convolution in fixed-point. N and r represent the number Instantaneous and inverse time protective algorithms are of samples and filter tap respectively. A fixed-point format executed to detect variety faults through relay co-ordination (type, W, F) in Fig.4 is composed of the data type, the property. number of total bits and the number of bits for fractional part, respectively. For example, (short, 12, 0) represents the 2.2 Target hardware specification corresponding data is a short integer type with 12-bit length and has no fractional bits. 12-bit ADC samples and In this paper, we employed TMS320C6416 processor previously stored DFT filter coefficients are calculated by based on Von Neumann architecture and only supporting convolution. Final outputs come out into 32 bits fixed-point. fixed-point operations by the hardware components. Fig 3 presents the detailed internal memory structure of the 2.4 CORDIC operations processor. TMS320C6416 processor is a VLIW architecture. Internal memory of processor consists of two-level cache Embedded software of the relay was implemented by hierarchical structures (Level 1 program cache memory 4KB applying COordinate Rotation DIgital Computing (CORDIC) (L1P), level 1 data cache memory 4KB (L1D) and 64KB algorithm [6] to compute main operations of RMS, phase RAM (L2)). Level 2 64KB RAM can be used in various ways and protective algorithm based on [3]. Including the such as program cache memory or data memory or mixture. trigonometric functions and various arithmetic operations can As shown in Fig. 3, DSP Core load 256 bits program code at be calculated by CORDIC. It is not an approximated method a clock from L1P, and 32 bits data from L1D. In case that to reduce amount of computation. CORDIC algorithm has advantages in terms of efficiency and accuracy. Table 1 shows the CORDIC operations for required arithmetic Interrupt Service Meters Instantaneous operations in this study. Each arithmetic operation can be Routine (Timer) Digital and Filter RMS, Inverse-time calculated by using specific CORDIC operational modes and Storing 12-bit ADC (DFT) Phase, Protective it might need additional constant multiplication or division samples Frequency Algorithms based on fixed-point depending on the type of operation. In addition, normalization and correction operations are required Fig. 2 Block Diagram for Digital Protective Relay S/W Fig. 3 Memory Structure for Target Signal Processor Fig. 4 Fixed-point design for convolution in DFT filter (int, 32, 11) (int, 32, 25) (int, 32, 25) (int, 32, 25) Xre X’re x0 Normali- zation xi, yi, zi xi+1, yi+1, zi+1 y + Xim X’im 0 CORDIC 0 z0 L-bit left shift, Sign makes X’im < 0.5 x31 z31 adjustment L-bit right RMS X shift Look-up table Arithmetic (int, 32, 11) (int, 32, 11) (int, 32, 25) f(i) (non-volatile shift memory) 2.3289 Phase (int, 32, 25) (int, 32, 25) Fig. 5 Fixed-point design for CORDIC operations Fig. 6 Fixed-point design for measuring RMS and Phase to guarantee the convergence of CORDIC iteration depending We adopted general inverse-time over current protection on the type of operation [3]. Fig. 5 illustrates the schematic of algorithm. Eq. (1) is a characteristic equation of the time- fixed-point design for main CORDIC operations. Normalized current curve. x, y, z for the convergence, are the inputs of the CORDIC -25 algorithm. Its precision ranges up to 2 and the number of the maximum iterations is 32. T = (1) 2.5 Measurement for RMS value and phase K and p are the constant representing the cut-off characteristics of the relay, Ir is the ratio of reference current Fig. 6 shows the RMS value and phase measurement to the fault current. Since p is a real number including process. Circular-vectoring mode of CORDIC operation is fractional number, the key point of the optimization is used for the measurement of RMS value as listed in Table 1. reduction in calculation time for exponentiation. There have L-bit shift operation will be added to imply proper correction been an approximated method to estimate quickly by after output z has been obtained from normalized input x and referencing lookup table (LUT) which implies the y. The phase measurement gets the output after the similar characteristic equation.