STV5348 STV5348/H - STV5348/T MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES FEATURES SUMMARY Figure 1. Package ■ COMPLETE TELETEXT AND VPS DECODER INCLUDING AN 8 PAGE MEMORY ON A SINGLE CHIP ■ UPWARD SOFTWARE COMPATIBLE WITH PREVIOUS ST’s MULTICHIP SOLUTIONS (SAA5231, SDA5243, STV5345) ■ PERFORM PDC SYSTEM A (VPS) AND PDC SYSTEM B (8/30/2) DATA STORAGE SEPARATELY PDIP28 (Plastic Package) ■ DEDICATED "ERROR FREE" OUTPUT FOR VALID PDC DATA ■ INDICATION OF LINE 23 FOR EXTERNAL USE ■ SINGLE +5V SUPPLY VOLTAGE ■ SINGLE 13.875MHz CRYSTAL ■ REDUCED SET OF EXTERNAL COMPONENTS, NO EXTERNAL SO28 (Plastic Package) ADJUSTMENT ■ OPTIMIZED NUMBER OF DIGITAL SIGNALS REDUCING EMC RADIATION Figure 2. Pin Connections ■ HIGH DENSITY CMOS TECHNOLOGY CVBS 1 28 CBLK ■ DIGITAL DATA SLICER AND DISPLAY CLOCK PHASE LOCK LOOP MA/SL 2 27 TEST ■ 28 PIN DIP & SO PACKAGE VDDA 3 26 VSSA POL 4 25 VSSO DESCRIPTION STTV/LFB 5 24 XTI The STV5348 decoder is a computer-controlled 6 23 teletext device including an 8 page internal mem- FFB XTO ory. Data slicing and capturing extracts the teletext VSSD 7 22 VDDD information embedded in the composite video sig- 8 21 nal. Control is accomplished via a two wire serial R VCR/TV 2 I C bus ®. Chip address is 22h. Internal ROM pro- G 9 20 RESERVED vides a character set suitable to display text using up to seven national languages. Hardware and B 10 19 DV software features allow selectable master/slave RGB REF 11 18 L23 synchronization configurations. The STV5348 also supports facilities for reception and display of BLAN 12 17 SDA current level protocol data. COR 13 16 SCL ODD/EVEN 14 15 Y REV. 2 May 2004 1/30 STV5348 - STV5348/H - STV5348/T Table 1. Pin Description Pin No Symbol Function Description Figure 1 CVBS Input Composite Video Signal Input through Coupling Capacitor 12 2 MA/SL Input Master/Slave Selection Mode 14 3VDDA Analog Supply +5V - 4 POL Input STTV / LFB / FFB Polarity Selection 15 5 STTV/LFB Output / Input Composite Sync Output, Line Flyback Input 18 6 FFB Input Field Flyback Input 15 7 VSSD Ground Digital Ground - 8 R Output Video Red Signal 16 9 G Output Video Green Signal 16 10 B Output Video Blue Signal 16 11 RGBREF Supply DC Voltage to define RGB High Level 16 12 BLAN Output Fast Blanking Output TTL Level 18 13 COR Output Open Drain Contrast Reduction Output 18 14 ODD/EVEN Output 25Hz Output Field synchronized for non-interlaced display 18 15 Y Output Open Drain Foreground Information Output 18 16 SCL Input Serial Clock Input 19 17 SDA Input/ Output Serial Data Input/Output 20 18 L23 Output Line 23 Identification 18 19 DV Output VPS Data Valid 18 20 RESERVED Test To be connected to VSSD through a resistor 18 21 VCR/TV Input PLL Time Constant Selection 18 22 VDDD Digital Supply +5V - 23 XTO Crystal Output Oscillator Output 13.875MHz 17 24 XTI Crystal Input Oscillator Input 13.875MHz 17 25 VSSO Ground Oscillator Ground - 26 VSSA Ground Analog Ground - 27 TEST Test Grounded to VSSA 14 28 CBLK Input / Output To connect Black Level Storage Capacitor 13 2/30 STV5348 - STV5348/H - STV5348/T Figure 3. Block Diagram STTV/LFB FFB MA/SL POL L23 VDDD VDDA 5 6 2 4 18 22 3 Data CVBS 1 CLAMPING DATA DECODING Clock SYNCHRONIZING DATA 19 DV CBLK 28 DATA EXTRACTION PROCESSING VCR/TV 21 20 TEST Data Address CTRL XTI 24 OSCILLATOR FREQUENCY 8 PAGES XTO 23 SYNTHETIZER MEMORY VSSO 25 TIME BASE 12 BLAN Data 13 COR Address CTRL SCL 16 2 8 RED I C BUS DISPLAY 9 GREEN INTERFACE INTERFACE SDA 17 10 BLUE 15 Y STV5348 7 26 27 11 14 VSSD VSSA TEST RGB REF ODD/EVEN Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit VDD Positive Supply Voltage on VDDD and VDDA –0.3, 6.0 V VI Input Voltage (any input) –0.3, VDD + 0.5 V VO Output Voltage (any output) –0.3, VDD + 0.5 V ∆VDD Difference between VDDD, VDDA 0.25 V Toper Operating Ambient Temperature 0, +70 °C Tstg Storage Temperature –40, +150 °C 3/30 STV5348 - STV5348/H - STV5348/T ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, TA = 25°C) Table 3. Supplies Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 4.75 5.0 5.25 V IDDD VDDD Pin Supply Current 30 mA IDDA VDDA Pin Supply Current 5 mA Table 4. Inputs Symbol Parameter Min. Typ. Max. Unit CBLK IBLKO Source Current (VCBLK = 2V, VCVBS = 0V) 4.75 5.0 5.25 V IBLKI Sink Current (VCBLK = 2V, VCVBS = 1V)) 30 mA CVBS CVBSI Video Input Amplitude (peak to peak) 1 V CVBSC Input Capacitance 10 pF tSYNC Delay from CVBS to TCS Output from STTV Pin 200 ns VCLAMP Clamping Level at Synchro Pulse 0 mV ICLPH High Level Clamp Current (CVBS = VCLAMP +1V) 5 µA ICLPL Low Level Clamp Current (CVBS = VCLAMP – 0.3V) –400 µA MA/SL, POL, LFB, FFB, VCR/TV VIL Input Voltage Low Level –0.3 +0.8 V VIH Input Voltage High Level 2 VDD V IIL Input Leakage Current (VI = 0 to VDDD) –10 +10 µA CI Input Capacitance 10 pF SCL, SDA VIL Input Voltage Low Level –0.3 +1.5 V VIH Input Voltage High Level 3 VDD V IIL Input Leakage Current (VI = 0 to VDD) –10 +10 µA fSCL Clock Frequency (SCL) 100 kHz tR, tF Input Rise and Fall Time (10 to 90%) 2 µs CI Input Capacitance 10 pF RGB REF VI Input Voltage VDD–0.5V VDD VDD+0.3V V II Input Current 50 mA 4/30 STV5348 - STV5348/H - STV5348/T Table 5. Outputs Symbol Parameter Min. Typ. Max. Unit RGB VOL Output Low Voltage (IOL = 2mA) 0.4 V VOH Output High Voltage (IOH = –2mA, RGB REF = VDD/2) RGB REF – 0.5 RGB REF V CL Load Capacitance 50 pF tR, tF Rise and Fall Time (10 to 90%) 20 ns BLAN VOL Output Low Voltage (IOL = 2mA) 0 0.4 V VOH Output High Voltage (IOH = –0.2mA) VDD – 0.5 V CL Load Capacitance 50 pF tR, tF Rise and Fall Time (10 to 90%) 20 ns ODD/EVEN, STTV, L23, DV VOL Output Low Voltage (IOL = 2mA) 0 0.5 V VOH Output High Voltage (IOH = –0.2mA) VDD – 0.8 VDD V CL Load Capacitance 50 pF tR, tF Rise and Fall Time (10 to 90%) 20 ns COR AND COR AND Y (with Pull up to VDDD) VOL Output Low Voltage (IOL = 2mA) 0 0.5 V CL Load Capacitance 25 V tF Fall Time (RL = 1.2kΩ, VDDD – 0.5V to 1.5V) 50 ns IOLL Output Leakage Current –10 +10 µs SDA VOL Output Low Voltage (IOL = 3mA) 0 0.5 V tF Fall Time (3.0 to 1.0V) 200 ns CL Load Capacitance 400 pF Table 6. Crystal Oscillator Symbol Parameter Min. Typ. Max. Unit fXTAL Crystal Frequency 13.875 MHz RBIAS Internal Bias Resistance 0.4 1 3 MΩ CI Input Capacitance 7 pF 5/30 STV5348 - STV5348/H - STV5348/T Table 7. Timing Symbol Parameter Min. Typ. Max. Unit SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) Clock: tLOW ● Low Period 4 µs ● tHIGH High Period 4 µs tSU, DAT Data Set-up Time 250 ns tHD, DAT Data Hold Time 170 ns tSU, STO Stop Set-up Time from Clock High 4 µs tBUF Start Set-up Time following a Stop 4 µs tHD, STA Start Hold Time 4 µs tSU, STA Start Set-up Time following Clock Low to High Transition 4 µs Figure 4. Display Output Timing LSP (TCS) 40µs 04.66 64 R.G.B.Y (1) 0 16.67 56.67 (a) LINE RATE all timings in µss lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R.G.B.Y (1) 0 41 291 312 (b) FIELD RATE line numbers 6/30 STV5348 - STV5348/H - STV5348/T Figure 5. Serial Bus Timing SDA t BUF t LOW t F SCL t HD,STA t R t HD,DAT t HIGH t SU,DAT SDA t SU,STA t SU,STO VIH = 3V , VIL = 1.5V Figure 6. Master Synchronization Mode - Hardware Configuration Output signal on STTV Pin : Synchro 1 Line PLL Line PLL POL grounded Extractor VCS when R1D2 = 0 TCS when R D = 1 MA/SL 1 2 VCS TCS 2 POL to VDD R1D2 = "0" R1D2 = "1" VCS when R D = 0 I2C 1 2 TCS when R D = 1 +5V Control 1 2 4 Bit R1D2 POL STTV 7/30 STV5348 - STV5348/H - STV5348/T Figure 7. Master Synchronization Mode - Delivered Composite Synchronization Signal VCS, TCS (interlaced) 621 622 623 624 625 12 3456 (308) (309) (310) (311) (312) VCS, TCS (interlaced) 309 310 311 312 313 314 315 316 317 318 319 (1) (2) (3) (4) (5) (6) TCS (non-interlaced) 308 309 310 311 312 1 2 3 4 5 6 The number positions indicate the end of lines. Internal signals : - VCS composite synchro from CVBS signal, - TCS Teletext composite synchro. Figure 8. Slave Synchronization Mode MA/SL LFB +5V 2 5 SCS +5V POL 4 6 FFB POL grounded, Inputs Signals : POL to VDD, Inputs Signals : are LFB line flyback synchro on Pin 5 are LFB line flyback synchro on Pin 5 FFB field flyback synchro on Pin 6 FFB field flyback synchro on Pin 6 or SCS synchro composite signal on Pins 5 and 6 or SCS synchro composite signal on Pins 5 and 6 Figure 9.