See all versions of this document Vivado Design Suite User Guide: Logic Simulation UG900 (v2019.2) October 30, 2019 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 10/30/2019 Version 2019.2 General updates Updated tables 7-2, 7-3, 7-4, A-6, and A-13. Compiling Simulation Libraries Added Riviera/Active-HDL: library.cfg file information. Supported Simulators Added table 1-1. Parsing Design Files, xvhdl and xvlog Updated xvlog Syntax. xelab Updated xelab Command Syntax Options. Appendix C: Universal Verification Methodology Support Added new appendix. 05/22/2019 Version 2019.1 General updates Updated tables 7-2,7-3, and B-2. Functional Coverage Report Generator Added new section. xelab Updated xelab Command Syntax Options. UG900 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Logic Simulation Overview............................................................... 7 Supported Simulators.................................................................................................................7 Simulation Flow .......................................................................................................................... 8 Language and Encryption Support ........................................................................................ 11 Chapter 2: Preparing for Simulation..................................................................12 Using Test Benches and Stimulus Files.................................................................................. 12 Pointing to the Simulator Install Location............................................................................. 13 Compiling Simulation Libraries............................................................................................... 14 Using Xilinx Simulation Libraries.............................................................................................19 Using Simulation Settings........................................................................................................ 28 Adding or Creating Simulation Source Files.......................................................................... 33 Generating a Netlist..................................................................................................................35 Chapter 3: Simulating with Third-Party Simulators................................. 38 Running Simulation Using Third Party Simulators with Vivado IDE................................... 38 Dumping SAIF for Power Analysis...........................................................................................41 Dumping VCD for Power Analysis........................................................................................... 43 Simulating IP..............................................................................................................................44 Using a Custom DO File During an Integrated Simulation Run.......................................... 44 Running Third-Party Simulators in Batch Mode....................................................................47 Chapter 4: Simulating with Vivado Simulator..............................................48 Running the Vivado Simulator.................................................................................................48 Running Functional and Timing Simulation...........................................................................66 Saving Simulation Results........................................................................................................ 68 Distinguishing Between Multiple Simulation Runs...............................................................69 Closing a Simulation................................................................................................................. 69 Adding a Simulation Start-up Script File.................................................................................70 Viewing Simulation Messages................................................................................................. 71 Using the launch_simulation Command................................................................................ 72 UG900 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 3 Re-running the Simulation After Design Changes (relaunch).............................................73 Using the Saved Simulator User Interface Settings..............................................................74 Chapter 5: Analyzing Simulation Waveforms with Vivado Simulator...................................................................................................................... 76 Using Wave Configurations and Windows.............................................................................76 Opening a Previously Saved Simulation Run.........................................................................77 Understanding HDL Objects in Waveform Configurations .................................................78 Customizing the Waveform..................................................................................................... 81 Controlling the Waveform Display ......................................................................................... 87 Organizing Waveforms.............................................................................................................91 Analyzing Waveforms............................................................................................................... 93 Analyzing AXI Interface Transactions..................................................................................... 98 Chapter 6: Debugging a Design with Vivado Simulator....................... 113 Debugging at the Source Level............................................................................................. 113 Forcing Objects to Specific Values.........................................................................................117 Power Analysis Using Vivado Simulator............................................................................... 125 Using the report_drivers Tcl Command................................................................................127 Using the Value Change Dump Feature...............................................................................127 Using the log_wave Tcl Command........................................................................................ 128 Cross Probing Signals in the Object, Wave, and Text Editor Windows.............................130 Chapter 7: Simulating in Batch or Scripted Mode in Vivado Simulator.....................................................................................................................136 Exporting Simulation Files and Scripts................................................................................. 136 Running the Vivado Simulator in Batch Mode.....................................................................142 Elaborating and Generating a Design Snapshot, xelab......................................................144 Simulating the Design Snapshot, xsim.................................................................................155 Example of Running Vivado Simulator in Standalone Mode............................................. 158 Project File (.prj) Syntax..........................................................................................................159 Predefined Macros.................................................................................................................. 160 Library Mapping File (xsim.ini).............................................................................................. 160 Running Simulation Modes....................................................................................................161 Using Tcl Commands and Scripts .........................................................................................164 export_simulation ...................................................................................................................165 export_ip_user_files.................................................................................................................168 UG900 (v2019.2) October 30, 2019Send Feedback www.xilinx.com Vivado Design Suite User Guide: Logic Simulation 4 Appendix A: Compilation, Elaboration, Simulation, Netlist, and Advanced Options..................................................................................................170 Compilation Options...............................................................................................................170 Elaboration Options................................................................................................................ 173 Simulation Options................................................................................................................. 174 Netlist Options.........................................................................................................................177 Advanced Simulation Options............................................................................................... 177 Appendix B: SystemVerilog Support in Vivado Simulator..................