USO09543378B2 (12) United States Patent (10) Patent No.: US 9,543,378 B2 Singh (45) Date of Patent: Jan. 10, 2017 (54) SEMICONDUCTOR DEVICES AND USPC ........................................... 257/25, 347, 402 FABRICATION METHODS THEREOF See application file for complete search history. (71) Applicant: GLOBALFOUNDRIES Inc., Grand (56) References Cited Cayman (KY) U.S. PATENT DOCUMENTS (72) Inventor: Jagar Singh, Clifton Park, NY (US) 4,940,671 A * 7/1990 Small ................ HO1L 21,82285 257 (491 (73) Assignee: GLOBALFOUNDRIES INC., Grand 8,610,241 B1* 12/2013 Hu ...................... HOL 270629 Cayman (KY) 257,353 2004/0095698 A1* 5, 2004 Gerrish ............... HOL27/O255 *) Notice: Subject to anyy disclaimer, the term of this 361 (91.1 patent is extended or adjusted under 35 2004/0253779 A1* 12/2004 Hong ............... HOL 21,8249 U.S.C. 154(b) by 10 days. 438,203 (21) Appl. No.: 14/467,420 * cited by examiner Primary Examiner — Kenneth Parker (22) Filed: Aug. 25, 2014 Assistant Examiner — Warren H Kilpatrick (65) Prior Publication Data (74) Attorney, Agent, or Firm — Heslin Rothenberg Farley & Mesiti P.C.; Kristian E. Ziegler US 2016/OO56231 A1 Feb. 25, 2016 (57) ABSTRACT (51) Int. Cl. Semiconductor devices and fabrication methods thereof are HOIL 29/06 (2006.01) provided. The semiconductor devices include: a substrate, HOIL 29/66 (2006.01) the Substrate including a p-type well adjoining an n-type HOIL 29/735 (2006.01) well; a first p-type region and a first n-type region disposed HOIL 29/47 (2006.01) within the n-type well of the substrate, where the first p-type HOIL 29/423 (2006.01) region at least partially encircles the first n-type region; and HOIL 29/08 (2006.01) a second p-type region and a second n-type region disposed HOIL 29/10 (2006.01) in the p-type well of the substrate, where the second n-type (52) U.S. Cl. region at least partially encircles the second p-type region. CPC ....... HOIL 29/0619 (2013.01); HOIL 29/0692 In one embodiment, the first p-type region fully encircles the (2013.01); HOIL 29/0821 (2013.01); HOIL first n-type region and the second n-type region fully 29/1008 (2013.01); HOIL 29/41708 (2013.01); encircles the second p-type region. In another embodiment, HOIL 29/42304 (2013.01); HOIL 29/6625 the semiconductor device may be a bipolar junction tran (2013.01); HOIL 29/735 (2013.01) sistor or a rectifier. (58) Field of Classification Search CPC ................................................... HO1L 29/0619 19 Claims, 5 Drawing Sheets COLLECTOR N-1 U.S. Patent Jan. 10, 2017 Sheet 1 of 5 US 9,543,378 B2 110 111 112 120 121 122 FIG. 1B U.S. Patent Jan. 10, 2017 Sheet 2 of 5 U.S. Patent Jan. 10, 2017 Sheet 3 of 5 US 9,543,378 B2 FIG. 1E 111 122 COLLECTOR COLLECTOR N-1 Nu1 102 FIG. 1F U.S. Patent Jan. 10, 2017 Sheet 4 of 5 US 9,543,378 B2 100 110 112 120 122 121 102 130 FIG. 1G 111 122 COLLECTOR COLLECTOR 102 FIG. 1H U.S. Patent Jan. 10, 2017 Sheet S of 5 US 9,543,378 B2 1OO 110 112 120 122 1-1 102 SECTION 1 3 O FIG. 1 111 122 FOURTH SECTION SECTION SECTION SECUON SECT9. SECUON 102 FIG. 1U US 9,543,378 B2 1. 2 SEMCONDUCTOR DEVICES AND FIG. 1B is a cross-sectional elevational view of the FABRICATION METHODS THEREOF structure of FIG. 1A, taken along line 1B-1B thereof, in accordance FIELD OF THE INVENTION with one or more aspects of the present invention; FIG. 1C is an isometric view of another embodiment of a The present invention relates to semiconductor devices structure including a semiconductor device, in accordance and methods of fabricating semiconductor devices. with one or more aspects of the present invention; FIG. 1D is a cross-sectional elevational view of the BACKGROUND OF THE INVENTION structure of 10 FIG. 1C, taken along line 1D-1D thereof, in accordance Modern integrated circuit designs may include a variety with one or more aspects of the present invention; of different semiconductor device types optimized for dif FIG. 1E is a plan view of one embodiment of a bipolar ferent functions. For example, field-effect transistors are junction transistor, in accordance with one or more aspects widely used to provide digital functions, such as logic, of the present invention; 15 FIG.1F is a cross-sectional elevational view of the bipolar memory, or processing. Other types of semiconductor junction transistor of FIG. 1E, taken along line 1F-1F devices, such as bipolar junction transistors and rectifiers, thereof, in accordance with one or more aspects of the are desirable to provide analog functions, such as tempera present invention; ture detection, electrostatic discharge protection, amplifica FIG. 1G is a plan view of one embodiment of a bipolar tion, or radio frequency functions. Therefore, integrated junction transistor, in accordance with one or more aspects circuits combining these different types of semiconductor of the present invention; devices to provide both analog and digital functions are FIG. 1H is a cross-sectional elevational view of the desirable. However, different device architectures of for bipolar junction transistor of FIG. 1G, taken along line example, field-effect transistors and bipolar junction tran 1H-1H thereof, in accordance with one or more aspects of sistors, typically require separate fabrication processes, 25 the present invention; leading to increased complexity and cost. FIG. 1I is a plan view of one embodiment of a semicon ductor controlled rectifier, in accordance with one or more BRIEF SUMMARY aspects of the present invention; and FIG. 1J is a cross-sectional elevational view of the semi The shortcomings of the prior art are overcome, and 30 conductor controlled rectifier of FIG. 1I, taken along line additional advantages are provided, through the provision, in 1J-1J thereof, in accordance with one or more aspects of the one aspect, of a semiconductor device. The semiconductor present invention. device includes: a Substrate, the Substrate including a p-type well adjoining an n-type well; a first p-type region and a first DETAILED DESCRIPTION n-type region disposed within the n-type well of the sub 35 strate, where the first p-type region at least partially encircles Aspects of the present invention and certain features, the first n-type region; and a second p-type region and a advantages, and details thereof, are explained more fully second n-type region disposed in the p-type well of the below with reference to the non-limiting examples illus Substrate, where the second n-type region at least partially trated in the accompanying drawings. Descriptions of well encircles the second p-type region. 40 known materials, fabrication tools, processing techniques, In another aspect, a method is presented. The method etc., are omitted so as not to unnecessarily obscure the includes providing a semiconductor device including a Sub invention in detail. It should be understood, however, that strate, the Substrate including a p-type well adjoining to an the detailed description and the specific examples, while n-type well. The providing includes: fabricating a first indicating aspects of the invention, are given by way of p-type region and a first n-type region disposed within the 45 illustration only, and not by way of limitation. Various n-type well of the Substrate, and a second p-type region and Substitutions, modifications, additions, and/or arrangements, a second n-type region disposed within the p-type well of the within the spirit and/or scope of the underlying inventive Substrate, where the first p-type region at least partially concepts will be apparent to those skilled in the art from this encircles the first n-type region, and the second n-type disclosure. region at least partially encircles the second p-type region. 50 In one implementation, an integrated circuit design may Additional features and advantages are realized through include multiple different device types at different locations the techniques of the present invention. Other embodiments to perform different functions. During integrated circuit and and aspects of the invention are described in detail herein semiconductor fabrication processing, millions, billions or and are considered a part of the claimed invention. more devices of these devices, such as transistors, capaci 55 tors, rectifiers, and resistors, may be formed to enable logic BRIEF DESCRIPTION OF THE SEVERAL circuits, memory storage elements, or analog components. VIEWS OF THE DRAWINGS The semiconductor fabrication process is very complex, and techniques that tend to reduce complexity can improve yield One or more aspects of the present invention are particu and reduce costs. Cost reductions may be achieved by, for larly pointed out and distinctly claimed as examples in the 60 example, the elimination or consolidation of process steps, claims at the conclusion of the specification. The foregoing or the simplification of designs. and other objects, features, and advantages of the invention For example, as described herein, several advantages may are apparent from the following detailed description taken in be realized by defining a single universal device design that conjunction with the accompanying drawings in which: may be adapted to act as multiple different device types, FIG. 1A is a plan view of one embodiment of a structure 65 leading to reduced design and maintenance costs. For including a semiconductor device, in accordance with one or instance, a universal design layout for multiple semiconduc more aspects of the present invention; tor devices may be developed to enable multiple different US 9,543,378 B2 3 4 devices.