Front cover IBM System z10 Enterprise Class Technical Guide Describes the Enterprise Class server and related features Addresses increasing complexity, rising costs, and energy contraints Discusses infrastructure for the data center of the future Per Fremstad Wolfgang Fries Marian Gasparovic Parwez Hamid Brian Hatfield Dick Jorna Fernando Nogal Karl-Erik Stenfors ibm.com/redbooks International Technical Support Organization IBM System z10 Enterprise Class Technical Guide November 2009 SG24-7516-02 Note: Before using this information and the product it supports, read the information in “Notices” on page xi. Third Edition (November 2009) This edition applies to the IBM System z10 Enterprise Class server, as described in IBM United States Hardware Announcement 108-794, dated October 21, 2008. © Copyright International Business Machines Corporation 2008, 2009. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . xi Trademarks . xii Preface . .xv The team who wrote this book . .xv Become a published author . xvii Comments welcome. xvii Chapter 1. Introducing the System z10 Enterprise Class . 1 1.1 Wanted: an infrastructure (r)evolution. 3 1.1.1 Simplified . 4 1.1.2 Shared . 4 1.1.3 Dynamic . 5 1.1.4 z10 at the core of a dynamic infrastructure. 6 1.1.5 Storage is part of the System z10 stack . 6 1.2 System z10 EC highlights . 7 1.3 System z10 EC Models. 9 1.3.1 Model upgrade paths . 10 1.3.2 Concurrent processing unit conversions. 10 1.4 System functions and features . 10 1.4.1 Processor . 12 1.4.2 Memory subsystem. 13 1.4.3 Central processor complex cage. 13 1.4.4 I/O connectivity . 14 1.4.5 I/O subsystems . 14 1.4.6 Cryptography . 16 1.4.7 Parallel Sysplex support . 17 1.4.8 Reliability, availability, and serviceability. 18 1.5 Performance . 19 1.6 Operating systems and software. 20 Chapter 2. Hardware components . 23 2.1 Frames and cages . 24 2.1.1 Frame A . 24 2.1.2 Frame Z . 26 2.1.3 I/O cages. 26 2.2 Book concept . 27 2.2.1 Book power . 28 2.2.2 Cooling . 28 2.3 Multi-Chip Module . 30 2.4 Processing units and storage control chips. 31 2.4.1 PU chip . 31 2.4.2 Processing unit (core) . 32 2.4.3 SC chip . 34 2.5 Memory . 35 2.5.1 Memory RAS. 38 2.5.2 Memory upgrades . 38 2.5.3 Book replacement and memory . 39 2.5.4 Flexible memory option. 39 © Copyright IBM Corp. 2008, 2009. All rights reserved. iii 2.5.5 Plan-ahead memory . 39 2.6 Connectivity. 41 2.6.1 Redundant I/O interconnect . 44 2.6.2 Enhanced book availability . 44 2.6.3 Book upgrade . 45 2.7 Model configurations . 45 2.7.1 Upgrades . 47 2.7.2 PU characterization. 48 2.7.3 Concurrent PU conversions . 48 2.7.4 Model capacity identifier . 49 2.7.5 Model capacity identifier and MSU values . 50 2.7.6 Capacity Backup . 51 2.7.7 On/Off Capacity on Demand and CPs . 53 2.8 Summary of z10 EC structure . 54 Chapter 3. System design . 57 3.1 Design highlights. 58 3.2 Book design . 59 3.2.1 Book interconnect topology. 64 3.2.2 System control . 65 3.3 Processing unit . ..