Intel® Xeon® Processor 7200 Series and 7300 Series Datasheet September 2008 Notice: The Intel® Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Document Number: 318080-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Copyright © 2006 - 2008, Intel Corporation 2 Document Number: 318080-002 Contents 1Introduction..............................................................................................................9 1.1 Terminology ..................................................................................................... 11 1.2 State of Data .................................................................................................... 13 1.3 References ....................................................................................................... 13 2 Electrical Specifications ........................................................................................... 15 2.1 Front Side Bus and GTLREF ................................................................................ 15 2.2 Decoupling Guidelines........................................................................................ 15 2.2.1 VCC Decoupling...................................................................................... 16 2.2.2 VTT Decoupling ...................................................................................... 16 2.2.3 Front Side Bus AGTL+ Decoupling ............................................................ 16 2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 16 2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0]).................................. 17 2.3.2 PLL Power Supply................................................................................... 17 2.4 Voltage Identification (VID) ................................................................................ 17 2.5 Reserved, Unused, or Test Signals....................................................................... 20 2.6 Front Side Bus Signal Groups.............................................................................. 20 2.7 CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 22 2.8 Test Access Port (TAP) Connection....................................................................... 22 2.9 Mixing Processors.............................................................................................. 23 2.10 Absolute Maximum and Minimum Ratings ............................................................. 23 2.11 Processor DC Specifications ................................................................................ 24 2.11.1 Flexible Motherboard Guidelines (FMB) ...................................................... 25 2.11.2 Platform Environmental Control Interface (PECI) DC Specifications................ 35 2.11.3 VCC Overshoot Specification .................................................................... 37 2.11.4 AGTL+ FSB Specifications........................................................................ 38 2.12 Front Side Bus AC Specifications ......................................................................... 40 2.13 Processor AC Timing Waveforms ......................................................................... 45 3 Mechanical Specifications ........................................................................................ 57 3.1 Package Mechanical Drawing............................................................................... 57 3.2 Processor Component Keepout Zones................................................................... 60 3.3 Package Loading Specifications ........................................................................... 66 3.4 Package Handling Guidelines............................................................................... 67 3.5 Package Insertion Specifications.......................................................................... 67 3.6 Processor Mass Specifications ............................................................................. 67 3.7 Processor Materials............................................................................................ 67 3.8 Processor Markings............................................................................................ 68 3.9 Processor Pin-Out Coordinates ............................................................................ 69 4 Pin Listing ............................................................................................................... 71 4.1 Pin Assignments................................................................................................ 71 4.1.1 Pin Listing by Pin Name........................................................................... 71 4.1.2 Pin Listing by Pin Number........................................................................ 79 5 Signal Definitions .................................................................................................... 87 5.1 Signal Definitions. ............................................................................................. 87 6 Thermal Specifications ............................................................................................ 95 6.1 Package Thermal Specifications........................................................................... 95 6.1.1 Thermal Specifications ............................................................................ 95 6.1.2 Thermal Metrology ............................................................................... 102 6.2 Processor Thermal Features.............................................................................. 103 6.2.1 Thermal Monitor Features...................................................................... 103 6.2.2 Thermal Monitor................................................................................... 103 Document Number: 318080-002 3 6.2.3 Thermal Monitor 2 ................................................................................ 104 6.2.4 On-Demand Mode................................................................................. 105 6.2.5 PROCHOT# Signal ................................................................................ 106 6.2.6 FORCEPR# Signal ................................................................................. 106 6.2.7 THERMTRIP# Signal .............................................................................. 106 6.3 Platform Environment Control Interface (PECI) .................................................... 107 6.3.1 Introduction......................................................................................... 107 6.3.2 PECI Specifications ............................................................................... 108 7Features................................................................................................................ 111 7.1 Power-On Configuration Options ........................................................................ 111 7.2 Clock Control and Low Power States..................................................................