TMS320C28x CPU and Instruction Set Reference Guide Literature Number: SPRU430F August 2001–Revised April 2015 Contents Preface....................................................................................................................................... 10 1 Architectural Overview........................................................................................................ 13 1.1 Introduction to the CPU ................................................................................................... 14 1.1.1 Compatibility With Other TMS320 CPUs ...................................................................... 14 1.1.2 Switching to C28x Mode From Reset .......................................................................... 14 1.2 Components of the CPU .................................................................................................. 15 1.2.1 Central Processing Unit (CPU) ................................................................................. 15 1.2.2 Emulation Logic ................................................................................................... 16 1.2.3 Signals ............................................................................................................. 16 1.3 Memory Map ............................................................................................................... 16 1.3.1 CPU Interrupt Vectors ........................................................................................... 17 1.4 Memory Interface .......................................................................................................... 18 1.4.1 Address and Data Buses ........................................................................................ 18 1.4.2 Special Bus Operations .......................................................................................... 19 1.4.3 Alignment of 32-Bit Accesses to Even Addresses ........................................................... 19 2 Central Processing Unit ...................................................................................................... 20 2.1 CPU Architecture .......................................................................................................... 21 2.2 CPU Registers ............................................................................................................. 23 2.2.1 Accumulator (ACC, AH, AL) ..................................................................................... 25 2.2.2 Multiplicand Register (XT) ....................................................................................... 26 2.2.3 Product Register (P, PH, PL) ................................................................................... 26 2.2.4 Data Page Pointer (DP) ......................................................................................... 27 2.2.5 Stack Pointer (SP) ................................................................................................ 28 2.2.6 Auxiliary Registers (XAR0-XAR7, AR0-AR7) ................................................................. 28 2.2.7 Program Counter (PC) ........................................................................................... 29 2.2.8 Return Program Counter (RPC) ................................................................................ 29 2.2.9 Status Registers (ST0, ST1) .................................................................................... 29 2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER) ........................................................... 29 2.3 Status Register ST0........................................................................................................ 30 2.4 Status Register ST1 ....................................................................................................... 41 2.5 Program Flow .............................................................................................................. 44 2.5.1 Interrupts ........................................................................................................... 44 2.5.2 Branches, Calls, and Returns ................................................................................... 44 2.5.3 Repeating a Single Instruction .................................................................................. 44 2.5.4 Instruction Pipeline ............................................................................................... 45 2.6 Multiply Operations ........................................................................................................ 45 2.6.1 16-bit × 16-bit Multiplication ..................................................................................... 45 2.6.2 32-Bit × 32-Bit Multiplication .................................................................................... 46 2.7 Shift Operations ............................................................................................................ 47 3 CPU Interrupts and Reset .................................................................................................... 52 3.1 CPU Interrupts Overview ................................................................................................. 53 3.2 CPU Interrupt Vectors and Priorities .................................................................................... 53 3.3 Maskable Interrupts: INT1–INT14, DLOGINT, and RTOSINT ....................................................... 55 3.3.1 CPU Interrupt Flag Register (IFR) .............................................................................. 55 3.3.2 CPU Interrupt Enable Register (IER) and CPU Debug Interrupt Enable Register (DBGIER) .......... 56 2 Contents SPRU430F–August 2001–Revised April 2015 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated www.ti.com 3.4 Standard Operation for Maskable Interrupts ........................................................................... 58 3.5 Nonmaskable Interrupts .................................................................................................. 62 3.5.1 INTR Instruction .................................................................................................. 62 3.5.2 TRAP Instruction .................................................................................................. 62 3.5.3 Hardware Interrupt NMI .......................................................................................... 64 3.6 Illegal-Instruction Trap .................................................................................................... 65 3.7 Hardware Reset (RS) ..................................................................................................... 65 4 Pipeline ............................................................................................................................. 67 4.1 Pipelining of Instructions .................................................................................................. 68 4.1.1 Decoupled Pipeline Segments................................................................................... 69 4.1.2 Instruction-Fetch Mechanism .................................................................................... 69 4.1.3 Address Counters FC, IC, and PC.............................................................................. 70 4.2 Visualizing Pipeline Activity ............................................................................................... 71 4.2.1 Example 4-2: Diagraming Pipeline Activity .................................................................... 71 4.2.2 Example 4-3 : Simplified Diagram of Pipeline Activity........................................................ 73 4.3 Freezes in Pipeline Activity ............................................................................................... 73 4.3.1 Wait States ......................................................................................................... 73 4.3.2 Instruction-Not-Available Condition ............................................................................. 74 4.4 Pipeline Protection ......................................................................................................... 74 4.4.1 Protection During Reads and Writes to the Same Data-Space Location .................................. 74 4.4.2 Protection Against Register Conflicts........................................................................... 75 4.4.3 Protection Against Interrupts..................................................................................... 76 4.5 Avoiding Unprotected Operations ........................................................................................ 76 4.5.1 Unprotected Program-Space Reads and Writes .............................................................. 76 4.5.2 An Access to One Location That Affects Another Location ................................................. 77 4.5.3 Write Followed By Read Protection Mode ..................................................................... 77 5 C28x Addressing Modes ..................................................................................................... 79 5.1 Type of Addressing Modes ............................................................................................... 80 5.2 Addressing Modes Select Bit (AMODE)................................................................................. 81 5.3 Assembler/Compiler Tracking of AMODE Bit..........................................................................