Intel® Quartus® Prime Standard Edition User Guide Getting Started Updated for Intel® Quartus® Prime Design Suite: 18.1 Subscribe UG-20173 | 2018.09.24 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® Quartus® Prime Standard Edition.................................................5 1.1. Selecting an Intel Quartus Prime Software Edition......................................................7 1.2. Introduction to Intel Quartus Prime Standard Edition Revision History...........................8 2. Managing Intel Quartus Prime Projects.......................................................................... 9 2.1. Viewing Basic Project Information.......................................................................... 10 2.1.1. Viewing Project Reports............................................................................ 11 2.1.2. Viewing Project Messages......................................................................... 12 2.2. Intel Quartus Prime Project Contents......................................................................13 2.2.1. Project File Best Practices..........................................................................14 2.3. Managing Project Settings.....................................................................................15 2.3.1. Specifying the Target Device or Board.........................................................16 2.3.2. Optimizing Project Settings....................................................................... 18 2.4. Managing Logic Design Files.................................................................................. 20 2.4.1. Including Design Libraries......................................................................... 21 2.4.2. Creating a Project Copy............................................................................ 21 2.5. Managing Timing Constraints.................................................................................21 2.6. Integrating Other EDA Tools.................................................................................. 22 2.7. Exporting Compilation Results............................................................................... 23 2.7.1. Exporting a Version-Compatible Compilation Database ................................. 24 2.7.2. Importing a Version-Compatible Compilation Database .................................24 2.7.3. Exporting a Design Partition...................................................................... 24 2.7.4. Clearing Compilation Results..................................................................... 25 2.8. Migrating Projects Across Operating Systems...........................................................26 2.8.1. Migrating Design Files and Libraries............................................................26 2.8.2. Design Library Migration Guidelines............................................................ 27 2.9. Archiving Projects................................................................................................ 28 2.9.1. Manually Adding Files To Archives.............................................................. 28 2.9.2. Archiving Compilation Results.................................................................... 29 2.9.3. Archiving Projects for Service Requests.......................................................29 2.9.4. Using External Revision Control..................................................................30 2.10. Command-Line Interface.....................................................................................31 2.10.1. Project Revision Commands.....................................................................31 2.10.2. Project Archive Commands...................................................................... 32 2.10.3. Project Database Commands................................................................... 32 2.10.4. Project Library Commands.......................................................................33 2.11. Managing Projects Revision History.......................................................................34 3. Design Planning............................................................................................................ 36 3.1. Design Planning...................................................................................................36 3.2. Create a Design Specification and Test Plan............................................................. 36 3.3. Plan for the Target Device..................................................................................... 36 3.3.1. Device Migration Planning......................................................................... 38 3.4. Plan for Intellectual Property Cores........................................................................ 38 3.5. Plan for Standard Interfaces..................................................................................39 3.6. Plan for Device Programming.................................................................................39 3.7. Plan for Device Power Consumption........................................................................40 3.8. Plan for Interface I/O Pins.....................................................................................42 Intel Quartus Prime Standard Edition User Guide: Getting Started Send Feedback 2 Contents 3.8.1. Simultaneous Switching Noise Analysis....................................................... 43 3.9. Plan for other EDA Tools....................................................................................... 44 3.9.1. Third-Party Synthesis Tools....................................................................... 44 3.9.2. Third-Party Simulation Tools...................................................................... 44 3.10. Plan for On-Chip Debugging Tools.........................................................................44 3.11. Plan HDL Coding Styles.......................................................................................45 3.11.1. Design Recommendations........................................................................46 3.11.2. Recommended HDL Coding Styles............................................................ 46 3.11.3. Managing Metastability........................................................................... 46 3.12. Plan for Hierarchical and Team-Based Designs........................................................47 3.12.1. Flat Compilation without Design Partitions................................................. 47 3.12.2. Incremental Compilation with Design Partitions.......................................... 48 3.12.3. Planning Design Partitions and Floorplan Location Assignments.....................48 3.13. Design Planning Revision History..........................................................................49 4. Introduction to Intel FPGA IP Cores..............................................................................52 4.1. IP Catalog and Parameter Editor............................................................................ 53 4.1.1. The Parameter Editor................................................................................53 4.1.2. Adding IP Cores to the IP Catalog...............................................................54 4.1.3. IP General Settings.................................................................................. 55 4.1.4. Installing and Licensing Intel FPGA IP Cores................................................ 56 4.1.5. Best Practices for Intel FPGA IP..................................................................59 4.2. Generating IP Cores (Intel Quartus Prime Standard Edition)...................................... 59 4.2.1. IP Core Generation Output (Intel Quartus Prime Standard Edition)..................60 4.3. Modifying an IP Variation...................................................................................... 61 4.4. Upgrading IP Cores.............................................................................................. 62 4.4.1. Upgrading IP Cores at Command-Line.........................................................64 4.4.2. Migrating IP Cores to a Different Device...................................................... 65 4.4.3. Troubleshooting IP or Platform Designer System Upgrade.............................. 66 4.5. Simulating Intel FPGA IP Cores.............................................................................. 68 4.5.1. Generating IP Simulation Files................................................................... 68 4.5.2. Using NativeLink Simulation (Intel Quartus Prime Standard Edition)................69 4.6. Synthesizing IP Cores in Other EDA Tools................................................................ 71 4.7. Instantiating IP Cores in HDL.................................................................................71 4.7.1. Example Top-Level Verilog HDL Module....................................................... 71 4.7.2. Example Top-Level VHDL Module................................................................71 4.8. Introduction to Intel FPGA IP Cores Revision History................................................. 72 5. Migrating to Intel Quartus Prime Pro Edition................................................................ 73 5.1. Keep Pro Edition Project Files Separate................................................................... 73 5.2. Upgrade Project Assignments and Constraints..........................................................73