EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends Some Recent Devices In production: In research: 65nm strained Si 10nm device Lg = 10 nm Corresponds to sub-22nm node (>10 years) 2 1 Some Recent Devices Intel’s 30nm transistor, circa 2002 Ion = 570μm/μm Ioff = 60nA/ μm [B. Doyle, Intel] 3 More Recent Devices Intel’s 20nm transistor, circa 2002 @0.75V [B. Doyle, Intel] 4 2 More Recent Devices Ultra-Thin-Body (UTB) MOSFET SOI: Silicon-on-Insulator [Choi, UCB] 5 18nm FinFET Double-gate structure + raised source/drain 400 -1.50 V Gate 350 Gate 300 -1.25 V Source Drain 250 -1.00 V Silicon 200 Fin [uA/um] -0.75 V BOX d Si fin - Body! I 150 -0.50 V 100 -0.25 V 50 0 X. Huang, et al, 1999 IEDM, p.67~70 -1.5 -1.0 -0.5 0.0 Vd [V] 6 3 Sub-5nm FinFET Lee, VLSI Technology, 2006 7 Major Roadblocks 1. Managing complexity How to design a 10 billion transistor chip? And what to use all these transistors for? 2. Cost of integrated circuits is increasing It takes >$10M to design a chip Mask costs are more than $3M in 45nm technology 3. The end of frequency scaling - Power as a limiting factor Dealing with leakages 4. Robustness issues Variations, SRAM, soft errors, coupling 5. The interconnect problem 8 4 Transistor Counts Transistor Counts in Intel's Microprocessors 1000 Itanium II 100 Pentium 4 Core2 ] Pentium II Itanium 10 Pentium Pro Pentium III Pentium Pentium MMX 486DX 1 486DX4 80286 386DX 0.1 8086 8088 Transistors [in millions [in Transistors Doubles every 2 years 0.01 8008 8080 4004 0.001 1970 1975 1980 1985 1990 1995 2000 2005 9 Frequency Frequency Trends in Intel's Microprocessors 10000 Pentium 4 Core2 Pentium III 1000 Itanium II Itanium Pentium II Pentium Pro 100 Pentium Pentium MMX 486DX 486DX4 80286 10 8086 386DX Frequency [MHz] 8088 Has been doubling 1 8080 every 2 years, 8008 but is now slowing down 0.1 4004 1970 1975 1980 1985 1990 1995 2000 2005 10 5 Power Dissipation Power Trends in Intel's Microprocessors 1000 Has been > doubling Itanium II Core 2 100 every 2 years Itanium Pentium 4 Pentium III Pentium Pro 10 Pentium Pentium II 80286 486DX Power [W] Power 8086 8088 1 386DX Has to stay 8008 8080 ~constant 4004 0.1 1970 1975 1980 1985 1990 1995 2000 2005 11 Active Power Scaling 1 1. If Vcc = 0.7, and Freq = ( ), 0.7 1 1 Power = CV 2 f = ( × 1.14 2 ) × (0.7 2 ) × ( ) = 1.3 0.7 0.7 2. If Vcc = 0.7, and Freq = 2, 1 Power = CV 2 f = ( × 1.14 2 ) × (0.7 2 ) × (2) = 1.8 0.7 3. If Vcc = 0.85 , and Freq = 2, 1 Power = CV 2 f = ( × 1.14 2 ) × (0.85 2 ) × (2) = 2.7 0.7 12 6 Microprocessor power 100 P6 Pentium ® proc 10 486 8086 286 386 8085 1 8080 Power (Watts) 8008 4004 0.1 S. Borkar 1999 1971 1974 1978 1985 1992 2000 Year LeadLead MicroprocessorsMicroprocessors powerpower continuescontinues toto increaseincrease 13 Power Will Be a Problem 100000 18KW 10000 5KW 1.5KW 1000 500W Pentium® proc 100 286 486 10 8086 386 Power (Watts) 8085 8080 8008 1 4004 S. Borkar 1999 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year PowerPower deliverydelivery andand dissipationdissipation willwill bebe prohibitiveprohibitive 14 7 Power Density Will Increase 10000 Sun’s Surface 1000 Rocket Nozzle Nuclear Reactor 100 8086 10 4004 Hot Plate P6 Power Density (W/cm2) Power Density 8008 8085 386 Pentium® proc 286 8080 486 S. Borkar 1 1999 1970 1980 1990 2000 2010 Year PowerPower densitydensity tootoo highhigh toto keepkeep junctionsjunctions atat lowlow temptemp 15 Power Delivery Challenges 1,000.00 1.E+07 1.E+06 100.00 1.E+05 1.E+04 10.00 P6 1.E+03 P6 Pentium® proc 1.E+02 8086 1.E+01 8086 Pentium® proc Icc (amp) Icc 1.00 386 386 486 486 L(di/dt)/Vdd 1.E+00 8080 286 8080 286 0.10 1.E-01 8085 8085 1.E-02 4004 8008 4004 1.E-03 8008 0.01 1.E-04 1970 1980 1990 2000 2010 1970 1980 1990 2000 2010 Year Year S. Borkar HighHigh supplysupply currentscurrents atat lowlow voltage:voltage: Challenges:Challenges: IRIR dropdrop andand L(di/dt)L(di/dt) noisenoise 16 8 The Power Challenge: Hottest chips published in ISSCC 1000 rs yea .4 / 3 100 x1 rs a e 10 y 3 / 4 x 1 Power per chip [W] 0.1 MPU DSP 0.01 1980 1985 1990 1995 2000 Year T. Kuroda, Keio University 17 Moore’s Law - Logic Density 1000 2 2x trend 100 Pentium II (R) 486 Pentium Pro (R) 10Logic Density 386 Pentium (R) i860 Logic Transistors/mm Logic Source: Intel Source: 1 S. Borkar 1.5μ 1.0μ 0.6μ 0.8μ 0.35μ 0.25μ 0.18μ 0.13μ ShrinksShrinks andand compactionscompactions meetmeet densitydensity goalsgoals NewNew micro-architecturesmicro-architectures dropdrop densitydensity 18 9 Die Size Growth 100 P6 486 Pentium ® proc 10 386 286 8080 8086 Die size (mm) 8085 ~7% growth per year 8008 4004 ~2X growth in 10 years S. Borkar 1 1970 1980 1990 2000 2010 Year DieDie sizesize growsgrows byby 14%14% toto satisfysatisfy Moore’sMoore’s LawLaw 19 Not Everything Scales G.E. Moore, ISSCC’03 20 10 Optical Lithography Issues Sub-wavelength lithography 1 1000 Lithography 365nm Wavelength 248nm 193nm nm micron 180nm 0.1 130nm Gap 100 90nm 65nm Generation 45nm 32nm 13nm EUV 0.01 10 1980 1990 2000 2010 2020 Source: Mark Bohr, Intel 21 Mask Costs 2500 45nm 2000 1500 65nm 1000 90nm Cost [in $1000] 0.13 μm 500 0.18 μm 0.25 μm 0 1996 1998 2000 2002 2004 2006 2008 Year MaskMask costscosts followfollow Moore’sMoore’s lawlaw asas wellwell 22 11 FAB Costs $100,000 Litho Cost $10,000 $1,000 $100 $10 Litho Tool Cost ($K) Tool Cost Litho G. Moore ISSCC 03 $1 1960 1970 1980 1990 2000 2010 $10,000 FAB Cost $1,000 $100 $10 Fab Cost ($M) Cost Fab www.icknowledge.com $1 1960 1970 1980 1990 2000 201023 Cost Increases Lithography is more complex Like “painting a 1cm line with a 3cm brush” 193nm laser Immersion Cost of exposure system Cost of proximity correction, phase shift masks Cost of mask repair But – mask costs drop in subsequent years Economic settings for maskless lithography Design costs increase with added complexity Chip starts ~$10M 24 12 Process Variations Control of minimum features does not track feature scaling Relative device/interconnect variations increase Sources: Lithography Feature size, oxide thickness variations Random dopant fluctuations Effects: Speed Power, primary leakage Yield 25 The Interconnect Scare 26 13 Technology Features EE 141 Technology vs. 45nm FEOL FEOL 0.25μm features 45nm technology Lg = 22μm Lg = 25nm 248nm lithography 192nm immersion lithography No OPC, liberal design rules OPC, restricted design rules SiO2 oxide, 3.5nm SiO2 oxide, 1.1nm 106 dopant atoms <103 dopant atoms Nobody knew what is ‘strain’ Strained silicon in channel Velocity saturated Velocity saturated No SD leakage IDS,off ~ 100nA No gate leakage Ig ~ 10nA One transistor flavor Many transistor flavors BEOL BEOL Al interconnect Cu interconnect SiO2 ILD Lo-k ILD 4-5 M layers 8-10 M layers No CMP, no density rules CMP, density rules 28 14 Strained Silicon PMOS High NMOS Stress Film SiGe SiGe Compressive channel strain Tensile channel strain 30% drive current increase 10% drive current increase in 90nm CMOS in 90nm CMOS 29 Strained Silicon No strain Strained Si VDD VDD M2 W2 = 2 M2 W = 1.6 In Out 2 In Out M1 W1 = 1 M1 W1 = 1 30 15 Next Lecture Device and gate models 31 16.