alMml digihl equipmentcorpomtion Copyright 1969 by Digital Equipment Corporation PDP is a registered trademark of Digital Equipment, Corporation The material in this handbook is for information pur- poses only and is subject to change without notice. TABLE OF CONTENTS CHAPIER 1 lNTRODUCTlOR PDP-11 SYSTEMS . .:.. 1 UNIBUS . , . 1 KAl 1 PROCESSOR . .?. 1 Priority Interrupts ,...............,..... 1 Reentrant Code . General Registers . :... 2 Instruction Set . .._........................................................ Addressing . ..~...............................................~........,...,......... z Asynchronous Operation . L 2 PACKAGJNG . ..I . 2 SOmARE ........................ .: ........................................................ 3 CHAPTER 2 SYSTEM INTRODUCTION SYSTEM DEFINITION .................................................................. 5 SYSTEM COMPONENTS ............................................................... 5 UNIBUS ................................................... .................................. 5 Single Bus ................................................................. .......... 5 Bidirectional Lines ............ .......................................... ..* .... 5 Master-Slave Relation ........................... .............................. 5 Interlocked .Communication ................................................ Dynamic Master-Slave Relation ........................................... : KAll CENTRAL PROCESSOR ...................................................... 6 General Registers ................................................................ l 6 Central Processor Status Register ........................................ 6 CORE MEMORY ............................................................................. 6 PERIPHERAL DEVICES ................................................................ 7 SYSTEM INTERACTION ................................................................ TRANSFER OF BUS MASTER ...................................................... 5 PRIORITY STRUCTURE ............ .................................................... 7 NPR Requests ....................................... .I ........................... Interrupt Requests .............................................................. : CHAPTER 3 ADDRESSING MODES INTRODUCTION ............................. ..................... .; ..................... 11 ADDRESS FIELDS ........................................................ ............... 11 General Register Addressing ....................... .:. ...................... 11 *Indexed Addressing ........................ ..................................... 12 Autoincrement Mode Addressing ........................................ 12 Autodecrement Addressing .................... ............................. 12 STACK PROCESSING .................................................................. 13 USE OF THE PC AS A GENERAL REGISTER .......................... _... 13 Immediate Addressing ......................................................... 13 Absolute Addressing ......................................................... .:. 13 Relative Addressing .............................................................. 14 Deferred Relative Addressing .......................................... ..:. 14 USE OF THE SP AS A GENERAL REGISTER ................................ 14 . DOUBLE OPERAND ADDRESSING .............................................. 14 &iAPTER 4 INSTRUCTlOil Sk INSTRUCTION TIMING ................................................................ 17 NOTATION .................................................................................... 17 Ill . DOUBLE OPERAND-INSTRUCTIONS .......................... i.. ............... 17 Arithmetic Operations .................. 1........................................ 18 Boolean Instructions ............................................................. 20 BRANCHES .......................................................................... .:. ..... 21 Unconditional Branch .......................................................... I Simple Conditional Branches .............................................. ;: Signed Conditional Branches .............................................. 23 Unsigned Conditional Branches .......................................... JUMP .................................................................................... 9: SUBROUTINES ............................................................................. 27 Examples ............................................................................ 28 SINGLE OPERAND INSTRUCTIONS ............................................ Multiple Precision Operations .............................................. zi Rotates ................................................................................ 33 Shifts .................................................................................. 34 Examples ............................................................................ 36 BYTE OPERATIONS ...................................................................... 36 Double Operand Byte Instructions ...................................... 36 Example .......... ................................................................... 37 Single Operand Instructions ................................................ 38 CONDITION CODE OPERATORS ................................................ MISCELLANEOUS CONTROL INSTRUCTIONS .............................. , i! PROCESSOR TRAPS .................................................................... 41 Trap Instructions ............................ ................................... 41 Stack Overflow Trap ............................................................ Bus Error Traps .................................................................. ii Trace Traps .......................................................................... 43 CHAPTER 5 I ADDRESS ALLOCATION ADDRESS MAP ............................................................................ 45 Interrupt and Trap Vector .................................................... 46 Processor Stack and General Storage .................................. Peripheral Registers ............................................................ z CORE MEMORY ............................................................................ 46 Read-Write Core Memory .................................. , ................. 46 Read-Only Core Memory ...................................................... g Wordlet Memory .................................................................. CHAPTER 6 PROGRAMMING OF PERIPHERALS DEViCE REGISTERS ...................................................... ..... ......... ;; - CONTROL & STATUS REGISTERS ............................................... Device Function Bits ....................................... :.. ................ $ Memory Extension ....................................................... ...... Done Enable and Interrupt Enable ...................................... Condition Bits ............................................................. ..i .... ii Unit Bits .............................................................................. g Error Bits .............. I ..:. ......................................................... DATA BUFFER REGISTERS .................................................. .: ...... 48 PROGRAMMING EXAMPLES--NON INTERRUPT ........................ 48 INTERRUPT STRUCTURE ............................................................ 50 PROGRAMMING EXAMPLE .......................................................... 51 CHAPTER 7 PERIPHERAL BULLETINS . TELETYPE (MODEL LT33-DC/DD) .............................................. ;; Size ...................................................................................... Power Requirement ............................................................ 53 IV . \ TELETYPE CONTROL (MODEL KLll) ......................................... 53 Teletype Control .......................................................... r ....... 53 Keyboard/Reader Operation ................................................ 53 Registers (TKS, TKB) .................................................. 54 Teleprinter/Punch ................................................................ 54 Registers (TPS, TPB) .................................................... .55 Programming Example ........................................................ 55 Peripheral Address Assignments .......................................... 55 Mounting ...................................... ....................................... 55 HIGH-SPEED PERFORATED TAPE READER (MODEL PCll) ...... 55 Tape Reader ........................................................................ 55 Registers (PRS, PRB) ................................................... 56 Programming Example ................................................ 56 Peripheral Address Assignments ................................ 56 Tape Punch .......................................................................... 56 Registers (PPS, PPB) .................. ., ................................ 57 Programming Example ................................................ Peripheral Address Assignments .................................. E Mounting ............................................................................... 57 Environmental ....................................................................... 58 Line Frequency Clock (Model KWll-L) ...........