MicroBlaze Processor Reference Guide Embedded Development Kit EDK 7.1i UG081 (v5.0) January 20, 2005 R © 2005 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. MicroBlaze Processor Reference Guide www.xilinx.com UG081 (v5.0) January 20, 2005 1-800-255-7778 MicroBlaze Processor Reference Guide UG081 (v5.0) January 20, 2005 The following table shows the revision history for this document. Date Version Revision 10/01/02 1.0 Xilinx EDK 3.1 release 03/11/03 2.0 Xilinx EDK 3.2 release 09/24/03 3.0 Xilinx EDK 6.1 release 02/20/04 3.1 Xilinx EDK 6.2 release 08/24/04 4.0 Xilinx EDK 6.3 release 09/21/04 4.1 Minor corrections for EDK 6.3 SP1 release 11/18/04 4.2 Minor corrections for EDK 6.3 SP2 release 01/20/05 5.0 Xilinx EDK 7.1 release UG081 (v5.0) January 20, 2005 www.xilinx.com MicroBlaze Processor Reference Guide 1-800-255-7778 MicroBlaze Processor Reference Guide www.xilinx.com UG081 (v5.0) January 20, 2005 1-800-255-7778 Table of Contents Preface: About This Guide Manual Contents. 7 Additional Resources . 7 Conventions . 8 Typographical. 8 Online Document . 9 Chapter 1: MicroBlaze Architecture Overview . 11 Features . 11 Data Types and Endianness . 12 Instructions . 13 Registers . 19 General Purpose Registers . 19 Special Purpose Registers . 20 Pipeline Architecture. 25 Branches. 26 Memory Architecture. 26 Reset, Interrupts, Exceptions and Break. 27 Reset . 28 Hardware Exceptions . 28 Breaks . 28 Interrupt . 29 User Vector (Exception) . 30 Instruction Cache . 30 Overview . 30 Instruction Cache Organization . 31 General Instruction Cache Functionality . 31 Instruction Cache Operation . 32 Instruction Cache Software Support . 32 Data Cache. 33 Overview . 33 Data Cache Organization . 33 General Data Cache Functionality . 34 Data Cache Operation . 35 Data Cache Software Support . 35 Floating Point Unit (FPU) . 36 Overview . 36 Format . 36 Rounding . 37 Operations . 37 Exceptions . 38 Fast Simplex Link (FSL) . 38 Hardware Acceleration using FSL. 38 MicroBlaze Processor Reference Guide www.xilinx.com 5 UG081 (v5.0) January 20, 2005 1-800-255-7778 R Debug and Trace . 39 Debug Overview . .39 Trace Overview . 39 Chapter 2: MicroBlaze Signal Interface Description Overview . 41 Features . 41 MicroBlaze I/O Overview . 41 On-Chip Peripheral Bus (OPB) Interface Description . 44 Local Memory Bus (LMB) Interface Description . 45 LMB Signal Interface . 45 LMB Transactions . .47 Read and Write Data Steering . 49 Fast Simplex Link (FSL) Interface Description . 50 Master FSL Signal Interface . 50 Slave FSL Signal Interface . 51 FSL Transactions . 51 Xilinx CacheLink (XCL) Interface Description . 51 CacheLink Signal Interface . ..