I • , _ "-f ' - inter i860™ XP MICROPROCESSOR • Parallel Architecture that Supports Up III Compatible with Industry Standards to Three Operations per Clock - ANSIIIEEE Standard 754-1985 for - One Integer or Control Instruction Binary Floating-Point Arithmetic - Up to Two Floating-Point Results -Intel 386™lintei 486™/i860TM Data Formats and Page Table Entries III High Performance Design - 40/50 MHz Clock Rate - Binary Compatible with i860™ XR -100 Peak Single Precision MFLOPS Applications Instruction Set - 75 Peak Double Precision MFLOPS - Detached Concurrency Control Unit - 64-Bit External Data Bus (CCU) Supports Parallel Architecture - 64-Bit Internal Code Bus Extensions (PAX) -128-Bit Internal Data Bus - JEDEC 262-pin Ceramic Pin Grid Array Package III High Integration on One Chip -IEEE Standard 1149.1/D6 Boundary­ - 32-Bit Integer and Control Unit Scan Architecture - 32/64-Bit Pipelined Floating-Point - 64-Bit 3-D Graphics Unit III Easy to Use - Paging Unit with 64 Four-Kbyte and - On-Chip Debug Register 16 Four-Mbyte Pages -UNIX'/860 - 16 Kbyte Code Cache - APX Attached Processor Executive - 16 Kbyte Data Cache - Assembler, Linker, Simulator, Debugger, C and FORTRAN III Fast, Multiprocessor-Oriented Bus Compilers, FORTRAN Vectorizer, - Burst Cycles Move 400 MbytelSec Scalar and Vector Math Libraries - Hardware Cache Snooping - Graphics Libraries - MESI Cache Consistency Protocol - Supports Second-Level Cache - Supports DRAM The Intel i860 XP Microprocessor (order code A80860XP) delivers supercomputing performance in a single VLSI component. The 32/64-bit architecture of the i860 XP microprocessor balances integer, floating point, and graphics performance for applications such as engineering workstations, scientific computing, 3-D graph­ ics workstations, and multiuser systems. Its parallel architecture achieves high throughput with RiSe design techniques, multiprocessor support, pipelined processing units, wide data paths, large on-chip caches, 2.5 million transistor design, and fast 0.8-micron silicon technology. A31 - A3 063 - DO CONTROL 240874-1 Figure 0.1. Block Diagram 'UNIX is a registered trademark of UNIX System Laboratories, Inc. Intel, i860, Intel386 and Intel486 are trademarks of Intel Corporation. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published speCifications on these devices from Intel. May 1991 © INTEL CORPORATION. 1991 Order Number: 240874-001 i860™ XP MICROPROCESSOR CONTENTS PAGE CONTENTS PAGE 2.4.4.6 Accessed and Dirty 1.0 FUNCTIONAL DESCRIPTION ......... 9 Bits ............................ 26 2.0 PROGRAMMING INTERFACE ........ 10 2.4.4.7 Page Tables for Trap Handlers ....................... 26 2.1 Data Types ......................... 10 2.4.4.8 Combining Protection of 2.1.1 Integer ........................ 10 Both Levels of Page Tables .... 26 2.1.2 Ordinal ........................ 10 2.4.5 Address Translation 2.1.3 Single- and Double-Precision Algorithm ......................... 26 Real .............................. 10 2.4.6 Address Translation Faults .... 27 2.1.4 Pixel .......................... 11 2.5 Detached CCU ..................... 27 2.2 Register Set ........................ 12 2.5.1 DCCU Initialization ............. 27 2.2.1 Integer Register File ........... 12 2.5.2 DCCU Addressing ............. 27 2.2.2 Floating-Point Register File .... 12 2.5.3 DCCU Internals ................ 28 2.2.3 Processor Status Register ..... 13 2.6 Instruction Set ...................... 28 2.2.4 Extended Processor Status 2.6.1 Pipelined and Scalar Register .......................... 14 Operations ....................... 30 2.2.5 Data Breakpoint Register ...... 16 2.6.1.1 Scalar Mode .............. 31 2.2.6 Directory Base Register ........ 16 2.6.1.2 Pipelining Status 2.2.7 Fault Instruction Register ...... 17 Information .................... 31 2.2.8 Floating-Point Status 2.6.1.3 Precision in the Register .......................... 17 Pipelines ....................... 31 2.2.9 KR, KI, T, and MERGE 2.6.1.4 Transition between Registers ......................... 19 Scalar and Pipelined 2.2.1 a Bus Error Address Operations ..................... 31 Register .......................... 20 2.6.1.5 Pipelined Loads .......... 32 2.2.11 Privileged Registers .......... 20 2.6.2 Dual-Instruction Mode ......... 32 2.2.12 Concurrency Control 2.6.3 Dual-Operation Instructions .... 33 Register .......................... 20 2.7 Addressing Modes ................. 34 2.2.13 NEWCURR Register ......... 21 2.8 Traps and Interrupts ................ 34 2.2.14 STAT Register ............... 21 2.8.1 Trap Handler Invocation ....... 34 2.3 Addressing ......................... 21 2.8.2 Instruction Fault ............... 34 2.4 Virtual Addressing .................. 22 2.8.2.1 Lock Protocol ............. 35 2.4.1 Page Frame ................... 22 2.8.2.2 Using PT and PI Bits ...... 35 2.4.2 Virtual Address ................ 23 2.8.3 Floating-Point Fault ............ 36 2.4.3 Page Tables ................... 23 2.8.3.1 Source Exception 2.4.4 Page-Table Entries ............ 24 Faults .......................... 36. 2.4.4.1 Page Frame Address ..... 24 2.8.3.2 Result Exception 2.4.4.2 Present Bit ...•........... 25 Faults .......................... 36 2.4.4.3 Writable and User Bits .... 25 2.8.4 Instruction Access Fault ....... 37 2.4.4.4 Write-Through Bit ......... 25 2.8.5 Data Access Fault ............. 37 2.4.4.5 Cache Disable Bit ......... 25 2.8.6 Parity Error Trap ............... 38 2.8.7 Bus Error Trap ................. 38 2 CONTENTS PAGE CONTENTS PAGE 2.8.8 Interrupt Trap .................. 38 4.2.11 ClK (Clock) .................. 51 2.8.9 Reset Trap .................... 38 4.2.12 CTYP (Cycle Type) ........... 52 2.9 Debugging ......................... 38 4.2.13 D/C# (Data/Code) .......... 52 4.2.14063-00 (Data Pins) .......... 52 3.0 ON-CHIP CACHES ................... 39 4.2.15 DP7 -DPO (Data Parity) ....... 52 3.1 Address Translation Caches ........ 39 4.2.16 EADS # (External Address 3.2 Internal Instruction and Data Status) ........................... 52 Caches .................. , ........... 41 4.2.17 EWBE # (External Write 3.2.1 Data Cache ................... 42 Buffer Empty) ..................... 52 3.2.1.1 Data Cache Update 4.2.18 FLlNE# (Flush Line) ......... 52 Policies ........................ 42 4.2.19 HIT# (Cache Inquiry Hit) ..... 53 3.2.2 Instruction Cache .............. 43 4.2.20 HITM# (Hit Modified 3.2.3 Cache Replacement Line) .............................. 53 Algorithm ......................... 43 4.2.21 HlDA (Bus Hold 3.2.4 Cache Consistency Acknowledge) .................... 53 Protocol .......................... 43 . 4.2.22 HOLD (Bus Hold) ............. 53 3.2.4.1 Data Cache States ........ 43 4.2.23 INV (Invalidate) ............... 53 3.2.4.2 Write-Once Policy ........ 44 4.2.24 INT /CS8 (Interrupt/Code- 3.2.4.3 locked Access ........... 44 Size Eight Bits) ................... 53 3.3 Internal Cache Consistency ......... 45 4.2.25 KBO, KB1 (Cache Block) ...... 54 3.3.1 Address Space 4.2.26 KEN # (Cache Enable) ....... 54 Consistency ...................... 45 4.2.27 lEN (Data length) ........... 54 3.3.2 Instruction Cache Consistency ...................... 46 4.2.28 lOCK # (Address lock) ...... 54 3.3.3 Page Table Consistency ....... 46 4.2.29 MIIO# (Memory-I/O) ........ 55 3.3.4 Consistency of 4.2.30 NA # (Next Address Cacheability ...................... 47 Request) ......................... 55 3.3.5 load Pipe Consistency ........ 47 4.2.31 NENE# (Next Near) .......... 55 3.3.6 Summary ...................... 47 4.2.32 PCD (Page Cache Disable) .......................... 55 4.0 HARDWARE INTERFACE ............ 47 4.2.33 PCHK# (Parity Check) ....... 55 4.1 Pins Overview ...................... 47 4.2.34 PCYC (Page Cycle) ........... 56 4.2 Signal Description .................. 50 4.2.35 PEN # (Parity Enable) ........ 56 4.2.1 A31-A3 (Address Pins) ........ 50 4.2.36 PWT (Page 4.2.2 ADS# (Address Status) ....... 50 Write-Through) ................... 56 4.2.3 AHOlD(Address Hold) ........ 50 4.2.37 RESET (System Reset) ....... 56 4.2.4 BE7#-BEO# 4.2.38 RSRVD, SPARE .............. 56 (Byte Enables) .................... 50 4.2.39 TCK (Test Clock) ............. 56 4.2.5 BERR (Bus Error) .............. 50 4.2.40 TDI (Test Data Input) ......... 56 4.2.6 BOFF # (Back-Off) ............ 50 4.2.41 TOO (Test Data Output) ...... 56 4.2.7 BRDY# 4.2.42 TMS (Test Mode Select) ...... 56 (Burst Ready) ..................... 51 4.2.43 TRST# (Test Reset) ......... 57 4.2.8 BREQ (Bus Request) .......... 51 4.2.44 Vcc (System Power) and Vss 4.2.9 BYPASS# (Bypass) ........... 51 (Ground) .......................... 57 4.2.10 CACHE # (Cacheability) ...... 51 4.2.45 VccClK (Clock Power) ....... 57 3 CONTENTS PAGE CONTENTS PAGE 4.2.46 WB/WT # (Write-Back/ Write-Through) ................... 57 6.0 TESTABILITY ........................ 87 4.2.47 W/R# (Write/Read) ......... 57 6.1 Test Architecture ................... 87 6.2 Test Data Registers ................ 87 5.0 BUS OPERATION .................... 57 6.3 Instruction Register ................. 88 5.1 Bus Cycles ......................... 57 6.4 TAP Controller ..................... 89 5.1.1 Single-Transfer Cycle .......... 58 6.4.1 Test-Logic-Reset State ........ 89 5.1.2 Burst Cycles ................... 58 6.4.2 Run-Test/Idle State ........... 90 5.1.3 Pipelined Cycles ............... 61 6.4.3 Select-DR-Scan State ........