Intel® Quartus® Prime Standard Edition Handbook Volume 3 Verification Updated for Intel® Quartus® Prime Design Suite: 17.1 Subscribe QPS5V3 | 2017.11.06 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1 Simulating Intel FPGA Designs.......................................................................................11 1.1 Simulator Support.................................................................................................11 1.2 Simulation Levels..................................................................................................12 1.3 HDL Support........................................................................................................ 12 1.4 Simulation Flows...................................................................................................13 1.5 Preparing for Simulation........................................................................................ 14 1.5.1 Compiling Simulation Models...................................................................... 14 1.6 Simulating Intel FPGA IP Cores............................................................................... 15 1.6.1 Generating IP Simulation Files.................................................................... 15 1.6.2 Scripting IP Simulation.............................................................................. 17 1.7 Using NativeLink Simulation (Intel Quartus Prime Standard Edition).............................24 1.7.1 Setting Up NativeLink Simulation (Intel Quartus Prime Standard Edition)..........25 1.7.2 Running RTL Simulation (NativeLink Flow)....................................................25 1.7.3 Running Gate-Level Simulation (NativeLink Flow).......................................... 26 1.8 Running a Simulation (Custom Flow)....................................................................... 26 1.9 Document Revision History.....................................................................................27 2 ModelSim - Intel FPGA Edition, ModelSim, and QuestaSim Support*..............................29 2.1 Quick Start Example (ModelSim with Verilog)............................................................29 2.2 ModelSim, ModelSim-Intel FPGA Edition, and QuestaSim Guidelines.............................30 2.2.1 Using ModelSim-Intel FPGA Edition Precompiled Libraries............................... 30 2.2.2 Disabling Timing Violation on Registers........................................................ 30 2.2.3 Passing Parameter Information from Verilog HDL to VHDL.............................. 31 2.2.4 Increasing Simulation Speed...................................................................... 31 2.2.5 Simulating Transport Delays....................................................................... 31 2.2.6 Viewing Simulation Messages..................................................................... 32 2.2.7 Generating Power Analysis Files.................................................................. 33 2.2.8 Viewing Simulation Waveforms................................................................... 33 2.2.9 Simulating with ModelSim-Intel FPGA Edition Waveform Editor........................34 2.3 ModelSim Simulation Setup Script Example.............................................................. 34 2.4 Unsupported Features........................................................................................... 35 2.5 Document Revision History.....................................................................................35 3 Synopsys VCS and VCS MX Support................................................................................37 3.1 Quick Start Example (VCS with Verilog)................................................................... 37 3.2 VCS and QuestaSim Guidelines...............................................................................37 3.2.1 Simulating Transport Delays....................................................................... 38 3.2.2 Disabling Timing Violation on Registers........................................................ 38 3.2.3 Generating Power Analysis Files.................................................................. 39 3.3 VCS Simulation Setup Script Example......................................................................39 3.4 Document Revision History.....................................................................................40 4 Cadence* Incisive Enterprise (IES) Support.................................................................. 41 4.1 Quick Start Example (NC-Verilog)............................................................................41 4.2 Cadence Incisive Enterprise (IES) Guidelines............................................................ 42 4.2.1 Using GUI or Command-Line Interfaces....................................................... 42 4.2.2 Elaborating Your Design............................................................................. 42 4.2.3 Back-Annotating Simulation Timing Data (VHDL Only)....................................43 Intel® Quartus® Prime Standard Edition Handbook Volume 3 Verification 2 Contents 4.2.4 Disabling Timing Violation on Registers........................................................ 43 4.2.5 Simulating Pulse Reject Delays................................................................... 43 4.2.6 Viewing Simulation Waveforms................................................................... 44 4.3 IES Simulation Setup Script Example.......................................................................44 4.4 Document Revision History.....................................................................................45 5 Aldec* Active-HDL and Riviera-PRO Support..................................................................46 5.1 Quick Start Example (Active-HDL VHDL).................................................................. 46 5.2 Aldec Active-HDL and Riviera-PRO Guidelines........................................................... 47 5.2.1 Compiling SystemVerilog Files.................................................................... 47 5.2.2 Simulating Transport Delays....................................................................... 47 5.2.3 Disabling Timing Violation on Registers........................................................ 47 5.3 Using Simulation Setup Scripts............................................................................... 48 5.4 Document Revision History.....................................................................................48 6 Design Debugging Using In-System Sources and Probes............................................... 49 6.1 Hardware and Software Requirements..................................................................... 51 6.2 Design Flow Using the In-System Sources and Probes Editor.......................................51 6.2.1 Instantiating the In-System Sources and Probes IP Core................................ 52 6.2.2 In-System Sources and Probes IP Core Parameters........................................53 6.3 Compiling the Design............................................................................................ 53 6.4 Running the In-System Sources and Probes Editor.................................................... 54 6.4.1 In-System Sources and Probes Editor GUI.................................................... 54 6.4.2 Programming Your Device With JTAG Chain Configuration............................... 54 6.4.3 Instance Manager..................................................................................... 55 6.4.4 In-System Sources and Probes Editor Pane...................................................55 6.5 Tcl interface for the In-System Sources and Probes Editor.......................................... 57 6.6 Design Example: Dynamic PLL Reconfiguration......................................................... 59 6.7 Document Revision History.....................................................................................61 7 Timing Analysis Overview.............................................................................................. 63 7.1 Timing Analysis Overview.......................................................................................63 7.2 Timing Analyzer Terminology and Concepts.............................................................. 63 7.2.1 Timing Netlists and Timing Paths.................................................................63 7.2.2 Clock Setup Check.................................................................................... 66 7.2.3 Clock Hold Check...................................................................................... 67 7.2.4 Recovery and Removal Time.......................................................................68 7.2.5 Multicycle Paths........................................................................................ 69 7.2.6 Metastability............................................................................................ 70 7.2.7 Common Clock Path Pessimism Removal...................................................... 71 7.2.8 Clock-As-Data Analysis.............................................................................. 72 7.2.9 Multicycle Clock Setup Check and Hold Check Analysis................................... 74 7.2.10 Multicorner Analysis.................................................................................77 7.3 Document Revision History.....................................................................................78