TECHNOLOGY ROADMAP DOCUMENT FOR SKA SIGNAL PROCESSING Document number .................................................................. WP2‐040.030.011‐TD‐001 Revision ........................................................................................................................... 1 Author ................................................................................................................ W.Turner Date ................................................................................................................ 2011‐02‐27 Status ....................................................................................................................... Issued Name Designation Affiliation Date Signature Additional Authors Submitted by: W. Turner Signal Processing SPDO 2011‐03‐26 Domain Specialist Approved by: P. Dewdney Project Engineer SPDO 2010‐03‐29 WP2‐040.030.011‐TD‐001 Revision : 1 DOCUMENT HISTORY Revision Date Of Issue Engineering Change Comments Number 1 ‐ ‐ First issue DOCUMENT SOFTWARE Package Version Filename Wordprocessor MsWord Word 2007 02‐WP2‐040.030.011.TD‐001‐1_SKATechnologyRoadmap Block diagrams Other ORGANISATION DETAILS Name SKA Program Development Office Physical/Postal Jodrell Bank Centre for Astrophysics Address Alan Turing Building The University of Manchester Oxford Road Manchester, UK M13 9PL Fax. +44 (0)161 275 4049 Website www.skatelescope.org 2011‐02‐27 Page 2 of 71 WP2‐040.030.011‐TD‐001 Revision : 1 TABLE OF CONTENTS 1 INTRODUCTION ............................................................................................. 9 1.1 Purpose of the document ....................................................................................................... 9 1.2 Technology Readiness Levels ................................................................................................ 10 2 REFERENCES .............................................................................................. 12 3 PROCESSING .............................................................................................. 14 3.1 General Purpose Processor ................................................................................................... 14 3.1.1 Theoretical Processing Performance ............................................................................ 17 3.1.2 Cost ............................................................................................................................... 17 3.1.3 Thermal Dissipation ...................................................................................................... 17 3.1.4 Scalability ...................................................................................................................... 18 3.2 Graphics Processing Unit ...................................................................................................... 19 3.2.1 Intel ............................................................................................................................... 19 3.2.2 ATI (AMD) ...................................................................................................................... 21 3.2.3 NVIDIA ........................................................................................................................... 22 3.2.4 Theoretical Processing Performance ............................................................................ 23 3.2.5 Cost ............................................................................................................................... 24 3.2.6 Thermal Dissipation ...................................................................................................... 24 3.3 Field Programmable Gate Array............................................................................................ 25 3.3.1 Theoretical Processing Performance ............................................................................ 28 3.3.2 Cost ............................................................................................................................... 28 3.3.3 Thermal Dissipation ...................................................................................................... 30 3.3.4 Hard Copy ...................................................................................................................... 31 3.4 Application Specific Integrated Circuit ASIC ......................................................................... 31 3.4.1 Process Size ................................................................................................................... 31 3.4.2 Masking Costs ............................................................................................................... 35 3.4.3 Yield and Die Costs ........................................................................................................ 35 3.4.4 Prototyping ................................................................................................................... 37 3.5 Gap between FPGAs and ASICS ............................................................................................. 37 3.5.1 Theoretical Processing Performance ............................................................................ 38 3.5.2 Cost ............................................................................................................................... 38 3.5.3 Thermal Dissipation ...................................................................................................... 39 3.6 Network on Chip, NoC........................................................................................................... 39 4 STORAGE .................................................................................................. 42 4.1 SRAM ..................................................................................................................................... 45 4.1.1 SRAM performance ....................................................................................................... 46 4.1.2 SRAM Thermal Dissipation ............................................................................................ 46 4.1.3 SRAM Cost ..................................................................................................................... 46 4.2 Dynamic Random Access Memory, DRAM ........................................................................... 46 2011‐02‐27 Page 3 of 71 WP2‐040.030.011‐TD‐001 Revision : 1 4.2.1 DRAM Performance ...................................................................................................... 47 4.2.2 DRAM Cost .................................................................................................................... 48 4.2.3 DRAM Thermal Dissipation ........................................................................................... 49 4.3 Flash Memory ....................................................................................................................... 50 4.3.1 NAND Cost ..................................................................................................................... 52 4.3.2 NAND Thermal Dissipation ............................................................................................ 52 4.4 Storage Class Memory .......................................................................................................... 52 4.4.1 SCM Performance ......................................................................................................... 53 4.4.2 SCM Cost ....................................................................................................................... 54 4.4.3 SCM Thermal Dissipation .............................................................................................. 54 5 DISK STORAGE ............................................................................................ 54 5.1.1 Disk Performance .......................................................................................................... 55 5.1.2 Disk Thermal Dissipation ............................................................................................... 56 5.1.3 Disk Cost ........................................................................................................................ 56 6 NETWORK ................................................................................................. 57 6.1 Infiniband .............................................................................................................................. 57 6.1.1 Infiniband Performance Roadmap ................................................................................ 57 6.1.2 Host Channel Adapters ................................................................................................. 58 6.1.3 Infiniband switches ....................................................................................................... 58 6.2 Ethernet ................................................................................................................................ 59 6.2.1 100 G bit/s Ethernet Switches ...................................................................................... 60 6.2.2 Terabit Ethernet ............................................................................................................ 60 6.2.3 Ethernet Cost ................................................................................................................ 60 6.2.4 Ethernet Thermal Dissipation ......................................................................................