1 SDP20 – TEAM 6 1 A. Significance CORDIC Resolve: A The resolver is chosen over a rotary or optical encoder in systems that must face rugged environments, such as extreme vibration or temperature. Our sponsor, L3Harris, uses resolver-to-digital resolvers in the defense industry, and our advisor, Prof. Frasier, uses resolvers to track the angular position of his solution using quadrature radar. Resolvers are also found in industrial applications, such as drilling [Yepez] and motor-controls [Szymczak]. More sampling. recently, IC design companies such as Texas Instruments and Analog Devices have cited resolvers for their future potential Jacob Andrade, EE, Meg Hardin, EE, Wayne Hobby, in control systems for fully-electric vehicles and robotics EE, and Kyle McWherter, EE [Verma], [Szymczak]. B. Context and Existing Products Abstract— At present, the angular position of a rotating ​ Put your problem in context. How have people solved your instrument is measured with a resolver. The output of a resolver is unintelligible to a computer, so a resolver-to-digital (RDC) problem in the past? Has the problem changed with time? converter is needed. This translates the resolver signals into Describe at least two products currently available that solve machine-readable language. There are two customers for this the same problem or a similar problem. What is different SDP project: L3Harris KEO and the UMass Amherst MIRSL about your proposed solution? Lab. For L3Harris, this project will be an RDC proof-of-concept. ● What’s an RDC chip, who makes them? Analog/TI For MIRSL, the project will be a flexible system to quickly and accurately convert any resolver signal for use in weather radar ● Going to try & solve with quadrature sampling tracking. Attached to a single or dual resolver, the final product instead → digital/analog mixed solution will output a measured angle to the user over multiple ● Quadrature sampling history, not a new solution communication methods. ● Introduce CORDIC algorithm ● Ultimate hope is that our solution will be more I. INTRODUCTION ​ FLEXIBLE, although this is a big goal The resolver is an analog sensor capable of angular and C. Societal Impacts velocity measurement of a rotating instrument. Inside of the sensor there are three coils: the primary winding, the sine Our winding and the cosine winding. The devices requires an input What are your constituencies? That is, who is impacted by sinusoid at some frequency θ which excites the primary your product, mostly in positive ways, but possibly others in winding. The mechanical angle ɸ of the primary winding negative ways? How are they impacted? How do these relative to the orthogonal sine and cosine windings produces constituencies affect your design choices? modulated output signals by inductive coupling. The input ● Making resolver use more accessible to signal to the resolver and resulting sine and cosine signals are non-engineers and low overhead industries. shown in equations x-x below. ● Go back to cited examples & explain importance, maybe draw back to TI and Analog both publishing (x1) V_input = sin(θt) papers in the past 5 years about resolvers used for (x2) V_sine = V_gain * sin(θt) * sin(ɸ) EVs (x3) V_cos = V_gain * sin(θt) * cos(ɸ) D. Requirements Analysis and Specifications Our project requirements are driven by our project goal of building a single RDC solution for any resolver configuration. Resolver’s have analog inputs and outputs, and so we included support for a wide range of voltage amplitudes and frequencies in our specifications. Our output communication, reporting frequency, angle precision, and reporting mode specifications were driven by requests from MIRSL. They wanted a product that could easily interface with their PC and could provide precise angle readings at short time increments. Finally, our reporting format specification was a request from 1 L3. F. A. Author from Lexington, Ma (e-mail: author@ boulder.nist.gov). S. B. Author, Jr., from Auburn, Ma (e-mail: [email protected]). T. C. Author from Quincy, Ma (e-mail: [email protected]). 2 SDP20 – TEAM 6 Table 1: Requirements and Specifications Specifications Value Notes Input Bare Wire Direct connection to Communication resolver output Output Ethernet/Serial Support Ethernet and a Communication Serial Output Excitation Variable, including Programmable excitation Frequency 60Hz and 8kHz +/- frequency for supporting 10% various resolvers Figure X: System block diagram. The grey block will become the required PCB component. Excitation Variable, including 4V Programmable excitation Amplitude and 120V RMS +/- amplitude for supporting B. System Architecture 10% various resolvers The system as built takes advantage of high speed analog to Reporting 100Hz MIRSL Specification digital sampling and FPGA processing available to engineers Frequency today to provide resolver to digital conversion. To start, the Precision Precision within 6 MIRSL Specification system’s output needs to be an angle. If a resolver’s function arcmin, 95% of the is seen as a vector rotating in a circle, then its outputs can be time seen to be its excitation signal scaled by the x and y components of the vector. This gives a resolver similar Reporting Modes Polling, Broadcast Allow passive vs active reporting properties to the unit circle. This relation is shown in image (x3). Reporting Binary Encoded Angle L3 Specification Format II. DESIGN A. Overview How will you solve this problem? What technology will you use? Why do you expect that this technology will solve your problem? What other technologies did you consider? Refer to the Appendix (Section A) for more details as needed. Include a block diagram as a figure and refer to it in the text as in “See the block diagram in Figure 1.” Do this for all ​ figures used in the report. Describe each block (and each arrow) in the diagram. What specifications will each block Image x3: Resolver Angle X and Y components meet? How do these specifications collectively guarantee that the system will meet the overall specifications? Given this observation, an ATAN2 function provides an Our resolver-to-digital solution will be rooted in digital ideal means of obtaining an angle since ATAN2 requires an x processing as opposed to and y component to produce an output angle and can be ● Merge digital & analog signal processing (identify implemented in an FPGA easily. One of the fastest and most when each is more useful) efficient ways to implement ATAN2 is using CORDIC. ○ ICs: analog needs CORDIC implements ATAN2 using a small look up table and ○ FPGA: close to hardware, CORDIC iteration to converge to an angle where every iteration ○ ARM: make FPGA “programmable”, UI corresponds to one bit of resolution. To provide x and y ○ Math: need to use everything correctly components for a CORDIC ATAN2 a method of sampling the ● Other options: all analog, mostly on ARM amplitudes of the sine and cosine outputs from the resolver ● Describe block diagram, connect to specs had to be chosen. Given that excessive noise on a resolver’s outputs could render the ATAN2 calculation worthless, a method of averaging collected samples was also needed. Quadrature sampling was selected as a preferable method to accomplish this task. Quadrature sampling is widely used in 3 SDP20 – TEAM 6 radio and telecommunications and for our purposes would be C. Digital Signal Processing used for its ability to distinguish small differences in a sinusoidal signal’s amplitude. One requirement for quadrature For digital signal processing in this project, we are using an sampling is multiplication of input signals by sine and cosine FPGA. For a detailed explanation of why we chose to use an signals. To obtain these signals in the digital domain the FPGA, see Appendix A. There are two functional blocks CORDIC algorithm was used once again. CORDIC sin/cos within the FPGA: generate and decode. The generate module generation operates in a similar way to CORDIC ATAN2 produces a digital sinusoid output with a specified frequency however instead of x and y inputs, it requires an angle as an in order to excite the primary winding of the resolver. The input. An added benefit of generating these signals that would decode module performs processing on the resolver sine and be taken advantage of was the need for an input excitation cosine signals in order to determine the mechanical angle of signal to power a resolver. To power a resolver a digital sine the resolver. These modules were developed separately, but signal from a CORDIC generator would be outputted to a the decode block uses the generation signal as input. See digital to analog converter and amplified. To further simplify figure x for a block diagram of the Verilog hierarchy. the design, the prototype would only use sine signal multiplication in the quadrature block. This was reasonable due to the fact that the resolver output signals would be relatively in phase with the sine quadrature multiplication signal since they all originate from the same CORDIC sin/cos generator. This means that for an effective prototype, full quadrature sampling using a cosine multiplication was not required as the resolver output signals would have no significant orthogonal component. After multiplication the results would then be accumulated. The following equations describe the contents of each accumulator. ∑ Sin(θr)Sin(φ) * Sin(φ) (x1) ∑ Cos(θr)Sin(φ) * Sin(φ) (x2) Figure x: Verilog hierarchy of generate and decode modules within the FPGA. In both equations x1 and x2 Sin(φ) represents the signal In order to implement the sine function in the generate from the CORDIC generation block. In equation equation x1 module, a counter produces evenly spaced x-values which are Sin(θr) represents the resolver sine output scaling. likewise in fed into a CORDIC IP core performing the sin(x) function. The increment of the counter will determine the frequency of equation x2 Cos(θr) represents the resolver cosine output signal scaling.