1 SDP20 – TEAM 6

1 A. Significance CORDIC Resolve: A The resolver is chosen over a rotary or optical encoder in systems that must face rugged environments, such as extreme vibration or temperature. Our sponsor, L3Harris, uses resolver-to-digital resolvers in the defense industry, and our advisor, Prof. Frasier, uses resolvers to track the angular position of his solution using quadrature radar. Resolvers are also found in industrial applications, such as drilling [Yepez] and motor-controls [Szymczak]. More sampling. recently, IC design companies such as Texas Instruments and Analog Devices have cited resolvers for their future potential Jacob Andrade, EE, Meg Hardin, EE, Wayne Hobby, in control systems for fully-electric vehicles and robotics EE, and Kyle McWherter, EE [Verma], [Szymczak]. B. Context and Existing Products Abstract— At present, the angular position of a rotating ​ Put your problem in context. How have people solved your instrument is measured with a resolver. The output of a resolver is unintelligible to a computer, so a resolver-to-digital (RDC) problem in the past? Has the problem changed with time? converter is needed. This translates the resolver signals into Describe at least two products currently available that solve machine-readable language. There are two customers for this the same problem or a similar problem. What is different SDP project: L3Harris KEO and the UMass Amherst MIRSL about your proposed solution? Lab. For L3Harris, this project will be an RDC proof-of-concept. ● What’s an RDC chip, who makes them? Analog/TI For MIRSL, the project will be a flexible system to quickly and accurately convert any resolver signal for use in weather radar ● Going to try & solve with quadrature sampling tracking. Attached to a single or dual resolver, the final product instead → digital/analog mixed solution will output a measured angle to the user over multiple ● Quadrature sampling history, not a new solution communication methods. ● Introduce CORDIC algorithm ● Ultimate hope is that our solution will be more I. INTRODUCTION ​ FLEXIBLE, although this is a big goal The resolver is an analog sensor capable of angular and C. Societal Impacts velocity measurement of a rotating instrument. Inside of the sensor there are three coils: the primary winding, the sine Our winding and the cosine winding. The devices requires an input What are your constituencies? That is, who is impacted by sinusoid at some frequency θ which excites the primary your product, mostly in positive ways, but possibly others in winding. The mechanical angle ɸ of the primary winding negative ways? How are they impacted? How do these relative to the orthogonal sine and cosine windings produces constituencies affect your design choices? modulated output signals by inductive coupling. The input ● Making resolver use more accessible to signal to the resolver and resulting sine and cosine signals are non-engineers and low overhead industries. shown in equations x-x below. ● Go back to cited examples & explain importance, maybe draw back to TI and Analog both publishing (x1) V_input = sin(θt) papers in the past 5 years about resolvers used for (x2) V_sine = V_gain * sin(θt) * sin(ɸ) EVs (x3) V_cos = V_gain * sin(θt) * cos(ɸ) D. Requirements Analysis and Specifications

Our project requirements are driven by our project goal of building a single RDC solution for any resolver configuration. Resolver’s have analog inputs and outputs, and so we included support for a wide range of voltage amplitudes and frequencies in our specifications. Our output communication, reporting frequency, angle precision, and reporting mode specifications were driven by requests from MIRSL. They wanted a product that could easily interface with their PC and could provide precise angle readings at short time increments. Finally, our reporting format specification was a request from 1 L3. F. A. Author from Lexington, Ma (e-mail: author@ boulder.nist.gov). S. B. Author, Jr., from Auburn, Ma (e-mail: [email protected]). T. C. Author from Quincy, Ma (e-mail: [email protected]). 2 SDP20 – TEAM 6

Table 1: Requirements and Specifications

Specifications Value Notes

Input Bare Wire Direct connection to Communication resolver output

Output Ethernet/Serial Support Ethernet and a Communication Serial Output

Excitation Variable, including Programmable excitation Frequency 60Hz and 8kHz +/- frequency for supporting 10% various resolvers Figure X: System block diagram. The grey block will become the required PCB component. Excitation Variable, including 4V Programmable excitation Amplitude and 120V RMS +/- amplitude for supporting B. System Architecture 10% various resolvers The system as built takes advantage of high speed analog to Reporting 100Hz MIRSL Specification digital sampling and FPGA processing available to engineers Frequency today to provide resolver to digital conversion. To start, the

Precision Precision within 6 MIRSL Specification system’s output needs to be an angle. If a resolver’s function arcmin, 95% of the is seen as a vector rotating in a circle, then its outputs can be time seen to be its excitation signal scaled by the x and y components of the vector. This gives a resolver similar Reporting Modes Polling, Broadcast Allow passive vs active reporting properties to the unit circle. This relation is shown in image (x3). Reporting Binary Encoded Angle L3 Specification Format

II. DESIGN A. Overview How will you solve this problem? What technology will you use? Why do you expect that this technology will solve your problem? What other technologies did you consider? Refer to the Appendix (Section A) for more details as needed. Include a block diagram as a figure and refer to it in the text as in “See the block diagram in Figure 1.” Do this for all ​ figures used in the report. Describe each block (and each arrow) in the diagram. What specifications will each block Image x3: Resolver Angle X and Y components meet? How do these specifications collectively guarantee that the system will meet the overall specifications? Given this observation, an ATAN2 function provides an Our resolver-to-digital solution will be rooted in digital ideal means of obtaining an angle since ATAN2 requires an x processing as opposed to and y component to produce an output angle and can be ● Merge digital & analog signal processing (identify implemented in an FPGA easily. One of the fastest and most when each is more useful) efficient ways to implement ATAN2 is using CORDIC. ○ ICs: analog needs CORDIC implements ATAN2 using a small look up table and ○ FPGA: close to hardware, CORDIC iteration to converge to an angle where every iteration ○ ARM: make FPGA “programmable”, UI corresponds to one bit of resolution. To provide x and y ○ Math: need to use everything correctly components for a CORDIC ATAN2 a method of sampling the ● Other options: all analog, mostly on ARM amplitudes of the sine and cosine outputs from the resolver ● Describe block diagram, connect to specs had to be chosen. Given that excessive noise on a resolver’s outputs could render the ATAN2 calculation worthless, a method of averaging collected samples was also needed. Quadrature sampling was selected as a preferable method to accomplish this task. Quadrature sampling is widely used in 3 SDP20 – TEAM 6 radio and telecommunications and for our purposes would be C. Digital Signal Processing used for its ability to distinguish small differences in a sinusoidal signal’s amplitude. One requirement for quadrature For digital signal processing in this project, we are using an sampling is multiplication of input signals by sine and cosine FPGA. For a detailed explanation of why we chose to use an signals. To obtain these signals in the digital domain the FPGA, see Appendix A. There are two functional blocks CORDIC algorithm was used once again. CORDIC sin/cos within the FPGA: generate and decode. The generate module generation operates in a similar way to CORDIC ATAN2 produces a digital sinusoid output with a specified frequency however instead of x and y inputs, it requires an angle as an in order to excite the primary winding of the resolver. The input. An added benefit of generating these signals that would decode module performs processing on the resolver sine and be taken advantage of was the need for an input excitation cosine signals in order to determine the mechanical angle of signal to power a resolver. To power a resolver a digital sine the resolver. These modules were developed separately, but signal from a CORDIC generator would be outputted to a the decode block uses the generation signal as input. See digital to analog converter and amplified. To further simplify figure x for a block diagram of the Verilog hierarchy. the design, the prototype would only use sine signal multiplication in the quadrature block. This was reasonable due to the fact that the resolver output signals would be relatively in phase with the sine quadrature multiplication signal since they all originate from the same CORDIC sin/cos generator. This means that for an effective prototype, full quadrature sampling using a cosine multiplication was not required as the resolver output signals would have no significant orthogonal component. After multiplication the results would then be accumulated. The following equations describe the contents of each accumulator.

∑ Sin(θr)Sin(φ) * Sin(φ) (x1)

∑ Cos(θr)Sin(φ) * Sin(φ) (x2) Figure x: Verilog hierarchy of generate and decode modules within the FPGA. In both equations x1 and x2 Sin(φ) represents the signal In order to implement the sine function in the generate from the CORDIC generation block. In equation equation x1 module, a counter produces evenly spaced x-values which are Sin(θr) represents the resolver sine output scaling. likewise in fed into a CORDIC IP core performing the sin(x) function. The increment of the counter will determine the frequency of equation x2 Cos(θr) represents the resolver cosine output signal scaling. While the contents of these accumulators do the output wave. Because the IP core only takes input values not directly represent the amplitude of either resolver output in the range [0, π/2], the counter must count both up and down signal, they do reflect the difference between their amplitudes. to produce the sine function from [0, π]. The wave processing Since ATAN2 only needs an x and y that are relatively sized module makes every other iteration of this process negative to in relation to each other, the accumulators hold all the produce a full period of the sine function. An unsigned version information needed. The last major signal processing of the generated sinusoid is sent to the breadboard to excite the challenge was that each accumulator was roughly sized to be resolver. capable of accumulating maximumly sized resolver output Next, a signed version of the generated wave and the sine signals for over 1 second resulting in 45 bit accumulators. and cosine outputs from the resolver are fed to the decode Using an ATAN2 function on 45 bit inputs was deemed module. The decode module instantiates two processing excessive and unnecessary and therefore a method of pathways, one for each resolver signal. First, the resolver and trimming the contents of the accumulators before ATAN2 was generated signal are multiplied together. Then, the output from required. This bit selection process would effectively remove the multiply block is accumulated until the control signal all sign extended bits until at least one input to ATAN2 had no requesting an angle report goes high. When a report request is sign extension. After the FPGA produces an angle from the made, the sine and cosine pathways empty their 54-bit resolver output signals it needs to be reported to a user. For the accumulated value into a window function. This module prototype, it was decided that the easiest way to accomplish selects which 16 bits from the accumulators should be sent to this was to use the available ARM processor on the acquired the ATAN2 function. The 16-bit window is chosen to SoC to report the angle to the Altera Monitoring Program. minimize the number of leading bits in the sine and cosine 4 SDP20 – TEAM 6 signals while keeping their ratio the same. This way, the this will be plugged into a serial-to-ethernet adapter in order to ATAN2 CORDIC IP core will decode the correct angle achieve both of the output communications listed in the regardless of how full the accumulators are at the time of specifications. report. Team members will have to learn how to leverage their The generate block was tested by connecting it’s output to a knowledge of serial communications from coursework to DAC using SPI. Signals at 60Hz and 10kHz were successfully implement a UI. Ethernet communication techniques were not produced. The functionality of the decode block was tested by covered on a hardware level, and so this will have to be creating an emulation of the resolver sine and cosine signals in learned along the way as well. In order to complete this block, the FPGA. In simulation, using the emulated resolver signals, a strong knowledge of Intel’s DE1-SOC tools will be required, the decode block was able to successfully decode 10 angles. the tools include: Quartus Prime II, Platform Designer Due to the fact that we had an ADC fail, we were not able to (QSYS), and ModelSim. These tools were introduced to some connect the decode block to the true resolver output during the of the team members in their coursework, however to MDR. See Appendix B for more information on testing complete this project that knowledge will have to be greatly methods. expanded upon. In order to test this block, the ARM will be set up to read a D. Analog Signal Processing hard coded value in the FPGA. Once the ARM is able to The analog signal processing block is the circuitry that takes successfully report this hard-coded value via the serial UI, that the 3.3V digital signals and interfaces them with the analog portion of this technical block’s functionality will have been resolver. There are two channels of communication, MOSI verified and the team can be confident that communications and MISO, where the FPGA is the master device and the from FPGA to ARM to UI are correct. resolver is the slave device. The initial signal is the MOSI signal, which comes through a SPI three-wire communication to the signal processing board. This data is sent to a DAC, III. PROJECT MANAGEMENT where a single tone is generated on the analog output pin. This Start with a table listing the status of your MDR goals. signal immediately goes to a unity gain buffer implemented on What have you accomplished? What is left to be done? a low-noise amplifier (NE5532). After this stage, the signal Describe the progress in more detail in the text of your report. goes through a second-order Butterworth HPF implemented Include a Gantt chart to demonstrate the work so far and the on the other channel of the NE5532. After this, the signal goes plan for the future. Indicate who has primary responsibility into a first-order RC LPF to tamp down some of the harmonic for each block and/or subsystem and who will be assisting. noise. The signal then goes into a LM675T Power Amplifier Describe any changes to team organization that you are to increase the amount of power that can be sent to the planning. Refer to Appendix (Section C) as needed. resolver. Once the signal gets through the resolver, there are ● Add MDR requirements table two signals coming out of it, which is the origin point of the ● Planned for full loop, didn’t quite make it MISO channel. These two differential signals are sent to a ● Explain hold-ups, but we will fix by New Years unity gain differential mode LNA, again using the NE5532. ● Add gantt chart, describe each person’s roles Now that the signals are referenced to ground, they can be ● Team organization change → primary & secondary properly formatted for the input of the ADCs. After the output responsibility for each item of gantt chart instead of of the LNAs, the signals go through a bias network which sets equal pairs the DC of each signal to 2.5V, and also gives a return signal ● Jacob to project management “leader”, Meg to that is a DC 2.5V signal. These four ports (two per channel) interpersonal “leader” are attached to the input of the ADCs, and the data is clocked out to the FPGA over SPI three-wire.

E. ARM/User-Interface IV. CONCLUSION The ARM/User-Interface technical block allows a user to Summarize the current state of the project. How did you get communicate to the FPGA what resolver configuration the there? Where are you going? RDC is being used on. It will then display the current angle of Describe your plans for the future? What difficulties do you the resolver to the user in one of the supported reporting expect? How will you get there? methods: on-demand angle report or constant angle reporting ● Supporting multiple resolvers could be really at 100Hz. challenging, big frequency/voltage range → full This technical block is implemented via the DE1-SOC and quadrature should help this it’s integrated ARM hard-processor system. The ARM will ● Rigorous gantt chart, reaching out to smart people, have to both read and set values in the FPGA. The C-code hard work → we will make it to FDR running on the ARM will include serial communications, and 5 SDP20 – TEAM 6

going to/from the different resolver types. Each of the various ACKNOWLEDGMENT voltage amplitude and frequency combinations had to be We would like to thank our industry sponsor, L3Harris, for consolidated to use the same digital IO to the DE1-SOC. their ideas and contributions throughout this project. In particular we acknowledge Greg Gottschalk for providing an B. Testing Methods architecture design, direct feedback and regular meetings with Our most challenging specification to test is precision. our team. We would also like to thank our advisor Prof. Currently, we have a test fixture built which rotates our Frasier for lending us a resolver and sharing his experiences resolver with a precision of 5 arcminutes. The benefit of this with resolvers used in radar. Furthermore, we thank fixture is that it tells us with high precision what angle we are AdvanTech International for donating a resolver to our group attempting to decode. Due to chip failure, we have yet to after learning about our project. resolve an angle with the test fixture and FPGA. However, once fully operational, we plan to extensively test the REFERENCES repeatability of our decoded result and ability to average out [1] R. Andraka, “A survey of CORDIC algorithms for FPGA based noise. The results of these experiments will determine what computers,” 1998. [2] B. Parhami, “The CORDIC Algorithms,” in Computer Arithmetic adaptations our system may need to meet end of academic Algorithms and Hardware Design, 2nd ed. New York Oxford University year requirements. The fixture itself was drafted in Press, 2010, pp. 459-471. Vectorworks CAD and printed at L3Harris using a [3] M. K. Patel, “FPGA designs with Verilog and SystemVerilog,” Markforged Mark 1 3D printer. The fixture is mounted on PythonDSP, Oct. 2018. optical alignment equipment sourced from L3Harris to assist [4] J. Szymczak, S. O’Meara, J. Gealon and C. N. De La Rama, “Precision in setup precision. Resolver-to-Digital Converter Measures Angular Position and Velocity,” We have also developed a Verilog module which emulates AnalogDialog, Analog Devices, Vol. 48, 2014. the resolver output by providing modulated sine and cosine [5] A. Verma and A. Chellamuthu, “Design considerations for resolver-to-digital converters in electric vehicles,” Analog Applications signals to the FPGA. When this emulator module is used, it Journal, Texas Instruments, AAJ 1Q, 2016. removes the resolver and analog circuitry from the system [6] J. Yepez, X. Shi and S.-B. Ko, “An FPGA-based Closed-loop Approach loop. The decode block is then used with this emulated of Angular Displacement for a Resolver-to-Digital-Convert,” IEEE, resolver to produce an output angle. In the future, we hope to 2018. analyze the output angles using the emulated resolver to [7] H. Zhang and Yanlan, “Design of Synchro Resolver-to-digital Converter evaluate how accurate the decode module is in isolation. Based on PXI Bus,” Pacific-Asia Conference of Knowledge Engineering Although small, there is some inaccuracy to be expected from and Software Engineering, 2009. the decode algorithm used in the FPGA. This is primarily due to the fact that the accumulator output is truncated to 16 bits APPENDIX before entering the ATAN2 function. A. Design Alternatives After doing the initial research on RDC’s, we discovered Table x: List of experiments to be performed with system. that most solutions today implement an RDC IC inside a Experiment Description primarily analog solution. This works well when trying to read a single resolver configuration, but completely lacks any kind Repeatability with Analyze repeatability of reports given fixed of flexibility in the form of support for other resolvers. fixed positions resolver positions. This will indicated the effects This led us to look into possible digital solutions, and so we of noise, phase lag, and distortion on the system since each report uses distinct sample sets. were introduced to the CORDIC algorithm. We hypothesized that by implementing the algorithm on a Microcontroller, we Repeatability with Analyze repeatability of reports given known could have achieved our end-goal of modularity. mechanical mechanical movement. This will confirm the While this might have worked, our sponsor L3 requested movement overall system’s ability to report consistent values within the tolerance of the mechanical fixture. that we implement the CORDIC algorithm on an FPGA in order to have more field-customizability. Upon further Emulated resolver Analyze reports using the emulated resolver. This consideration, we came to the conclusion that an ideal solution will indicate inaccuracy of the decode module in isolation. As updates are made to the decode would include an FPGA running the CORDIC algorithm, module next semester, we would like to track the alongside an ARM microprocessor used to run the serial and isolated inaccuracy of the decode module ethernet UI. This idea came to us due to some team members decrease. having experience with the DE1-SOC board. Once we had decided on this configuration, the remainder of the design decisions mostly related to the analog circuitry and how to C. Team Organization best support the wide range of analog IO which would be Our team’s organization has been largely determined by the 6 SDP20 – TEAM 6 roles that have been assigned to each member. Wayne is in D. Beyond the Classroom charge of the analog circuitry and the PCB. Meg has taken the lead in implementing the CORDIC algorithm via Verilog, Kyle - I have had to improve my understanding of discrete Jacob is responsible for serial communications, the time digital signal processing greatly. I had no understanding FPGA-ARM link, and the UI. Kyle has taken on a number of of quadrature sampling or how it worked at the beginning of roles including researching the CORDIC algorithm, verifying this project. I’ve have found engineers at L3Harris to be our implementation in MATLAB, and developing a test especially helpful in teaching me the necessary knowledge fixture to confirm the precision of our RDC. Over the needed to complete this project. I first approached engineers at semester, each member has had to develop the skills required L3Harris about collaboration on this project in the spring of to become an expert on their task. 2019 as prior internship related projects I had done there were Most of the collaborative work within our team has been challenging. At times, this project becomes hard to distinguish done in pairs. When Wayne needed support on the analog from other projects I worked on while employed with the circuitry, Kyle stepped up to get our breadboard design company. working by soldering our small MSOP package IC’s onto DIP Meg - Prior to this project, I had no experience working breakout boards. Kyle would also help Meg whenever she with FPGAs and only limited experience writing Verilog. As needed a deeper theoretical understanding of the CORDIC it became clear that my primary role in this project was algorithm. To get the FPGA-ARM link working, Meg would working with the FPGA, I got access to the projects from act as Jacob’s remote access to the FPGA hardware and ECE354 (Computers Systems Lab II) and began to familiarize provide support in the hardware design and C-code debugging myself with the Altera FPGA development and simulation process. software including Quartus II and ModelSim. I also found the This approach was advantageous because it allowed a document titled “FPGA designs with Verilog and significant amount of the development to occur in parallel. SystemVerilog” by Patel very useful. Furthermore, my However, it seemed that communication started to break down coursework this semester in VLSI and digital synthesis near the end of the semester when these parallel tasks needed complimented my role in this project well. This semester I was to be integrated. Once the FPGA design had gone through able to get a broad sense of how FPGAs work: theoretically, simulation and was ready for testing, there was a stall in functionally and practically. actually getting the analog circuit hooked up to the FPGA. Jacob - My role in this project has been very much centered When this happened, our team came together and made the around getting the DE1-SOC to communicate. This includes project work to the best of our abilities, but we all understood internal communications between the FPGA and the ARM, that with better communication we could have avoided most and also external communications with the custom circuit. of our problems. This has given me an opportunity to further develop the ability Throughout the semester, a sizeable portion of the team’s to navigate Intel software including Quartus Prime and interactions were based on preparing for and carrying out Platform Designer(QSYS). There are a number of concepts meetings with our SDP advisor and our L3 industry sponsor. having to do with SOC architecture that need to be well Our main form of communication has been through a text understood in order to establish a link between the FPGA and group chat where updates were provided on a need-to-know ARM. My main resources in completing this task have been basis with very little structure. This created a number of online resources from Intel, and my projects from ECE 354 challenges for us, especially considering the fact that Jacob Compsys Lab 2. Alongside learning how to use the SOC, I was working remotely due to his co-op. It became a struggle also needed to develop my knowledge of Verilog to keep him included in some of the spur-of-the-moment development, including the use of IP Cores. My main resource meetings that would sometimes occur after a class or just upon for this has been the Internet and the in-depth documentation meeting up in lab. Also, when taking into consideration included with the SPI communication IP core that I chose to everyone’s busy schedules, it became hard to set aside time for use. Currently the work I do at my company is more hardware meetings with just the group members. We all juggle many related, so developing these skills has been an exciting and responsibilities including industry employment and intensive inspiring experience for me. It has broadened my view of the coursework making our combined availability limited. industry and encouraged me to want to branch out in the After MDR, we had an honest and empathetic group future. meeting to reflect on our challenges and to create solutions for Wayne - My role in this project has been the analog better teaming practices next semester. Starting this spring, we circuitry for the signal processing board. This entails ensuring will have strict weekly team meetings, apart from our advisor the best possible signal quality throughout the circuit, and sponsor meetings, where we will set weekly goals for managing amplifiers and filtering where necessary, and which we are each held accountable. ensuring that power levels for the circuit were ample to drive the signal sizes that we needed. As far as all of the elements of design go, I received help from Kyle with some of the 7 SDP20 – TEAM 6 feedback networks, and I got the idea for the active filtering from Meg. I got some tips on chip selection from my internship, where I spend a great deal of time this past summer choosing them. The main skill that I needed to develop was problem solving, and how to get things working or decide that they’re busted once things go wrong.

E. Additional Appendix Section F. Additional Appendix Section