Effective Power/Ground Plane Decoupling for PCB Dr. Bruce Archambeault IBM Research Triangle Park, NC [email protected] Power/Ground-Reference Plane Noise • Must consider TWO Major Factors – Functionality -- Provide IC with sufficient charge – EMC -- Reduce noise along edge of board from IC somewhere else • Decoupling strategies are FULL of Myths Source of Power/Ground-Reference Plane Noise • Power requirements from IC during switching • Critical Net currents routed through via Power Bus Spectrum Clock Driver I DT74FCT807 Noise Injected between Planes Due to Critical Net Through Via (0,100)(Unit: mm) (150,100) y z x Edge voltage test point 1 (40,30) (112.5,25) (150,33.3) signal via I/O line via (0,0) (50,0) (150,0) Edge voltage test point 2 Zs=50 60 10 mils Vs GND + t signal line I/O line Vedge PWR _ 10 mils 60 Zant = 100 Transfer function from Via to I/O Pin -20 TM40 TM TM02 TM31 -25 TM10 11 TM01 -30 -35 -40 -45 -50 -55 Voltage Ratios (dB) Voltage -60 10 mils thickness 20 mils thickness -65 30 mils thickness 45 mils thickness -70 100 500 1000 1500 2000 2500 3000 Frequency (MHz) Decoupling Must be Analyzed in Different Ways for Different Functions •EMC – Resonance big concern – Requires STEADY-STATE analysis • Frequency Domain – Transfer function analysis • Eliminate noise along edge of board due to ASIC/IC located far away Decoupling Must be Analyzed in Different Ways for Different Functions • Provide Charge to ASIC/IC – Requires TRANSIENT analysis – Charge will NOT travel from far corners of the board fast enough – Local decoupling capacitors dominate – Impedance at ASIC/IS pins important Steady-State Analysis • Measurements and Simulations • Test Board with Decoupling capacitors every 1” square Test Board Ports 12” 11” #1 #2 #3 #4 #5 10” 9” #6 #7 #8 #9 #10 5” #11 #12 #13 #14 #15 1” 1” 3” Figure 1 6” 9” S21 Used for Decoupling “Goodness” • Ratio of Power ‘out’ to power ‘in’ • Better Indicator of EMI noise transmission across board • Also used to validate simulations Measured S21 for 12" x 10" PC Board Between Power/Ground Planes with No Decoupling Capacitors (Measured Center to Corner) 0 Board -10 Capacitance Dominates -20 -30 -40 S21 (dB) -50 -60 -70 Physical Board Size Resonances Dominate -80 0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) Test Board Decoupling Capacitor Placement for 25 .01 uf Caps Possible Cap Location Populated Cap Locations Test Board Decoupling Capacitor Placement for 51 .01 uf Caps Possible Cap Location Populated Cap Locations S21 Between Port #8 and Port #1 on Test Board With Various Amounts of .01 uf Decoupling Capacitors 0 -20 -40 -60 S21 (dB) No Caps -80 25 Caps 51 Caps -100 99 Caps -120 0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 Between Port #8 and Port #1 on Test Board With Various Amounts of .01 uf Decoupling Capacitors 0 No Caps -10 25 Caps 51 Caps -20 99 Caps -30 S21 (dB) -40 -50 -60 0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) 0.01uF Cap Impedance 22pF 0.01uF in parallel with 22pF 10000 1000 100 10 |Z| (Ohms) 1 0.1 1.00E+6 1.00E+7 1.00E+8 1.00E+9 1.00E+10 Freq (Hz) Test Board Decoupling Capacitor Placement for 41 22pf Caps (In Addition to 99 .01uf Caps) Possible Cap Location Populated Cap Locations S21 Between Port #8 and Port #1 on Test Board With 99 .01 uf Decoupling Capacitors and Various Amounts of 22pf Capacitors Added 0 -10 9 22pf Caps -20 17 22pf Caps 21 22pf Caps 33 22pf Caps -30 41 22pf Caps S21 (dB) 99 22pf Caps -40 99 Caps -50 -60 0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) Comparison of Model and Measured Data for 10" x 12" Board 0.0 99 caps -- alternating .01uF and 330pF -10.0 -20.0 -30.0 -40.0 -50.0 S21 (dB) -60.0 CIAO - .01uF & 330 pF Measured -70.0 -80.0 -90.0 -100.0 0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) S21 Transfer Function for Different Value Capacitors Center-to-Corner 0 10" x 12" Board -10 -20 -30 -40 S21 (dB) -50 99 .01uF caps 99 0.1uF caps -60 99 0.33uF caps 99 Caps (0.01uF and 330pF) -70 99 2nh shorts -80 0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) Voltage Distribution @ 350 MHz .01uF and 330pF Case (Source in Center) Voltage Distribution @ 750 MHz .01uF and 330pF Case (Source in Center) Voltage Distribution @ 950 MHz .01uF and 330pF Case (Source in Center) Voltage and Gradient 99 caps @ 800 MHz .01 uF Capacitor Impedance with 5/8” Trace 1000 pF Capacitor Impedance with 5/8” Trace 22 pF Capacitor Impedance with 5/8” Trace Other Design Possibilities • So-called Buried Capacitance – Reduces high frequency transfer function – Allows less capacitors to be used – Really should be called ‘increased distributed capacitance’ • Lossy decoupling – Reduces high frequency transfer function – Allows less capacitors to be used Buried Capacitance • Planes very close together (2 mils) • Only effective for the power/ground plane pair !!! • Other sets of Planes must still be decoupled the traditional way Buried Capacitance ONLY Applies to Plane Pairs Still Needs Decoupling Buried Capacitance Plane Pairs Transfer function for Decoupling Board 10" x 12" with Various Power/Ground Plane Separation and No Capacitors 0 -10 -20 -30 -40 -50 -60 Transfer function (dB) -70 2 mil - No Caps -80 10 mil - No Caps 20 mil - No Caps -90 35 mil - No Caps -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Ghz) Transfer function for Decoupling Board 10" x 12" with Various Power/Ground Plane Separation 0 -10 -20 -30 -40 -50 -60 Transfer function (dB) -70 2 mil - No Caps 10 mil - No Caps -80 20 mil - No Caps -90 35 mil - No Caps 35 mil w/99 caps -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Ghz) Lossy Decoupling • New technique • Series resistance and capacitance in same SMT package • Need to use both low ESR capacitors and lossy capacitors – fewer total parts Cause of Failure above 400 - 500 MHz? • Inductance is limiting factor for capacitors • Board size cause resonances which causes problems • Need to reduce resonance effects by lowering Q-factor – add resistive loss Modelled S21 Transfer Function 10"x12" Board R&C Decoupling (Port 8-to-1) -20.0 -30.0 -40.0 -50.0 Transfer Function (dB) -60.0 99 RC Terminations 99 .01uF caps Edge Term, 20 caps, 45 RCs -70.0 Edge Term, 35 caps, 30 RCs Edge Term, 49 caps, 14 RCs -80.0 0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) Transfer Function with Resistive Caps Port 8 to Port 1 (Resistive Caps with ~10 ohms and 0.01 uF) 0 -10 all 0.1 uF caps RC on outer edge only RC on two rows -20 RC on three rows RC alternating everywhere -30 -40 -50 Transfer Function (dB) -60 -70 -80 0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 2.0E+09 Frequency (Hz) Comparison of Impedance of SMT Capacitors Lossy and Normal Capacitor (0805 size) 100 Standard 0.01uF Capacitor Resistive 0.01uF capacitor 10 1 Impedance Magnitude (ohms) 0 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) Transient Analysis • Provide charge to ASIC/IC • Inductance dominates impedance – Loop area 1st order effect • Traditional analysis not accurate enough Traditional Analysis #1 • Use impedance of capacitors in parallel ESR1 ESR2 ESR3 ESR4 ESL1 ESL2 ESL3 ESL4 1uF 0. 1uF 0.01uF .001uF Impedance to IC power/gnd pins No Effect of Distance to IC Included! Traditional Impedance Calculation for Four Decoupling Capacitor Values 1000 100 .1uF .01uF .001uF .0001uF 10 All in Parallel 1 Impedance (ohms) 0.1 0.01 1.00E+07 1.00E+08 1.00E+09 Frequency (Hz) Traditional Analysis #2 • Calculate loop area – Traditional loop Inductance formulas – Which loop area? Which size conductor ESR1 ESR2 ESR3 ESR4 ESL1+Ld1 ESL2+Ld2 ESL3+Ld3 ESL4+Ld4 1uF 0. 1uF 0.01uF .001uF Impedance to IC power/gnd pins Over Estimates L and Ignores Distributed Capacitance More Accurate Model Includes Distributed Capacitance Intentional Decoupling Capacitors IC Power Pin Distributed capacitors Distributed Capacitance Schematic Intentional Capacitor Distributed Capacitance ESR Loop L Note: L increases Capacitance as distance from source increases Source Effect of Distributed Capacitance • Can NOT be calculated/estimated using traditional capacitance equation • Displacement current amplitude changes with position and distance from the source Displacement Current 500 MHz via @40 mils from Source Displacement Current 500 MHz via @40 mils from Source Displacement Current 500 MHz via @450 mils from Source Displacement Current 500 MHz via @450 mils from Source Displacement Current 800 MHz via @40 mils from Source Displacement Current 800 MHz via @40 mils from Source Displacement Current 800 MHz via @450 mils from Source Displacement Current 800 MHz via @450 mils from Source Need to Find the Real Effect of Decoupling Capacitor Distance • Perfect decoupling capacitor is a via between planes • FDTD simulation to find the effect of shorting via distance from source • Vary spacing between planes, distance to via, frequency, etc Impedance of Shorting Via vs.