A SPICE CMOS LEVEL-2, LEVEL-4, AND BSIM-PLUS MODEL FILES Computer-aided design tools have become indispensable in the integrated­ circuit design. The SPICE (Simulation Program with Integrated Circuit Em­ phasis) program [1, 2] has been widely accepted for circuit analysis since its introduction a decade ago. Circuit simulation execution time has been substan­ tially reduced through algorithm improvement and hardware enhancements in the past few years. Device modeling plays an important role in VLSI circuit design because computer-aided circuit analysis results are only as accurate as the models used. The SPICE2G6.B and SPICE 3F.3 programs have provided six built-in MOS transistor models [3]-[10]. The LEVEL-1 model, which contains fairly simple expressions, is most suitable for preliminary analysis. The LEVEL-2 model, which contains expressions from detailed device physics, is widely used for the analysis of analog circuits. Its accuracy is quite limited when small-geometry transistors are used. The LEVEL-3 model represents an early attempt to pursue the semi-empirical modeling approach, which only approximates device physics and relies on the proper choice of the empirical parameters to accurately repro­ duce device characteristics. The LEVEL-4 model, which is also called BSIM (Berkeley Short-Channel IGFET Model), is ideal for the simulation of digital and analog circuits with effective channel lengths as small as 0.8 J.lm. The LEVEL-5 model, which supports more than 100 device parameters, requires special care to use and very elaborated parameter extraction. The LEVEL-6 model is based on the empirical nth power law and specially optimized for quick estimation of digital circuit behavior. In addition, the BSIM_plus model has been developed at University of Southern California. It is a greatly enhanced version over the original LEVEL-4 model. 513 514 ApPENDIX A The modeling equations for the LEVEL-2 model can be found in the books by P. Antognetti and G. Massobrio [11] and by D. Divekar [12]. A set of typical parameter values for the LEVEL-2 model is listed in Table A.I. These parameter values were extracted from a 2-J,Lm double-polysilicon p-well CMOS process. The test wafers were fabricated by Orbit Semiconductor Inc. through The MOSIS Service at USC/Information Sciences Institute. Table A.1 Typical parameter values for the LEVEL-2 model. parameters symbols n-channel p-channel unit vtho VTO 0.888 -0.738 V T01! TOX 3.9E-8 3.9E-8 m Xj XJ 2.0E-7 2.0E-7 m N6Ub NSUB 2.2E+16 5.8E+15 em-Oj ~f PHI 0.6 0.6 V ,\ LAMBDA 0.028 0.058 V-I J,Lo UO 585 273 em2 /V - S J,Lcrit UCRIT 121762 57420 V/em J,Le1!p UEXP 0.221 0.255 - 'Y GAMMA 0.952 0.518 V l / 2 Vma1! VMAX 72452 36876 m/s Ld LD 2.1E-7 2.4E-7 m Gj CJ 4.06E-4 2.05E-4 F/m2 Mj MJ 0.46 0.45 - Gj6W CJSW 4.17E-I0 2.34E-IO F/m Mj6w MJSW 0.35 0.32 - GGDO CGDO 2.69E-IO 3.0IE-10 F/m GGSO CGSO 2.69E-IO 3.0lE-10 F/m GGBO CGBO 2.00E-IO 2.00E-IO F/m The modeling equations for the LEVEL-4 model can be found in [4]-[6]. The format of the parameters is listed below. TRANSISTORS name L sens. factor W sens. factor units of basic parameter I VPB (VFB) VPBI (LVFB) VPBw (WVFB) V 2 <Ps (PHI) <PSI (LPHI) <Psw (WPHI) V SPICE CMOS LEVEL-2J LEVEL-4J and BSIM_plus Model Files515 3 Kl (Kl) KlI (LKl) K lw (WKl) vt 4 K2 (K2) K21 (LK2) K2w (WK2) 5 TJo (ETA) TJOI (LETA) TJow (WETA) 6 jJz (MUZ) dl (DL) dw (DW) cm2/V - s (jJm, jJm) 7 Uoz (UO) UOZI (LUO) Uozw (WUO) V-l 8 Ulz (Ul) UlZI (LUI) UlZw (WUl) jJmV- l 9 jJZB (X2MZ) jJZBI (LX2MZ) jJZBw (WX2MZ) cm2/V2 - s 10 TJB (X2E) TJBI (LX2E) TJBw (WX2E) V-l 11 TJD (X3E) TJDI (LX3E) TJDw (WX3E) V-l 12 UOB (X2UO) UOB/ (LX2UO) UOBw (WX2UO) V-2 13 UlB (X2Ul) UlBI (LX2Ul) UlBw (WX2Ul) jJmV-2 14 jJs (MUS) jJSI (LMS) jJSw (WMS) cm2/V2 - s 15 jJSB (X2MS) jJSBI (LX2MS) jJSBw (WX2MS) cm2/V2 - s 16 jJSD (X3MS) jJSDI (LX3MS) jJSDw (WX3MS) cm2/V2 - s 17 UlD (X3Ul) UlDl (LX3Ul) UlDw (WX3Ul) jJmV-2 18 Tor (TOX) Temp (TEMP) Vdd (VDD) jJm(OC,v) 19 CGDO CsubGSO CGBO P/m 20 XsubPART DUMI DUM2 21 No NOI Now 22 NB NB/ N Bw 23 ND NDI NDw INTERCONNECTS 1 R.h (RSH) Cj (CJ) Cjw (CJW) Ijs (IJS) Pj (PJ) 2 Pjw (PJW) M j (MJ) Mjw (MJW) Wdf (WDF) dl (DL) The names of the process parameters of transistors are listed below: VFB flat-band voltage rPs surface inversion potential K 1 body effect coefficient K2 drain/source depletion charge sharing coefficient TJo zero-bias drain-induced barrier lowering coefficient jJz zero-bias mobility Uoz zero-bias transverse-field mobility degradation coefficient Ulz zero-bias velocity saturation coefficient jJZB sensitivity of mobility to the substrate bias at Vd. = 0 TJB sensitivity of drain-induced barrier lowering effect to the substrate bias TJD sensitivity of drain-induced barrier lowering effect to the drain bias, at Vd.= Vdd 516 ApPENDIX A UOB sensitivity of transverse-field mobility degradation effect to the substrate bias U1B sensitivity of velocity saturation effect to the substrate bias J-Ls mobility at zero substrate bias and at Vd, = Vdd J-LSB sensitivity of mobility to the substrate bias at Vd, = Vdd J-LSD sensitivity of mobility to the drain bias at Vd, = Vdd UlD sensitivity of velocity saturation effect to the drain bias, at Vd,= Vdd Tox gate-oxide thickness Temp temperature at which the process parameters are measured Vdd measurement bias range No zero-bias subthreshold slope coefficient N B sensitivity of subthreshold slope to the substrate bias N D sensitivity of subthreshold slope to the drain bias CaDo gate-drain overlap capacitance per meter channel width Caso gate-source overlap capacitance per meter channel width CaBO gate-bulk overlap capacitance per meter channel length XPART gate-oxide capacitance model flag Note: XPART= 0, 0.5, and 1 selects the 40/60, 50/50, and 0/100 channel­ charge partitioning methods, respectively. The names of the process parameters of diffusion layers are listed below: sheet resistance/square R,h fJ/square zero-bias bulk junction bottom capacitance/unit area Cj F/m 2 zero-bias bulk junction sidewall capacitance/unit length Cjw F/m bulk junction saturation current/unit area lj. A/m2 bulk junction bottom potential Pj V bulk junction sidewall potential Pjw V bulk junction bottom grading coefficient M·J bulk junction sidewall grading coefficient Mjw default width of the layer Wdf m average reduction of size due to side etching or mask compensation m The names of the process parameters of poly and metal layers are listed as following: sheet resistance/square fJ/square capacitance/unit area F/m 2 edge capacitance/unit length F/m default width of the layer m SPICE CMOS LEVEL-2, LEVEL-4, and BSIM_plus Model Files517 average variation of size due to side etching or mask compensation m The following is an example of a parameter set from The MOSIS Service. The lines starting with "*,, are used as comments. NM1 PM1 DU1 DU2 ML1 ML2 *PROCESS=hp *RUN=n29z *WAFER=2 *Gate-oxide thickness= 176.0 angstroms *Geometries (W-drawn/L-drawn, units are f.lm/ f.lm) of transistors measured were: * 1.5/1.0,3.0/1.0,9.0/1.0,3.0/3.0, 3.0/9.0 *Bias range to perform the extraction (VDD) = 5 volts *DATE=02-11-93 *NMOS PARAMETERS -7.58998E-01, 2.14897E-02, 1.23152E-01 7.42201E-01, O.OOOOOE+OO, -2.83200E-24 8.90900E-01, -3.11958E-02, -3.54696E-01 7.88072E-02, 5.78136E-02, -1. 73583E-01 -2.99119E-03, 2.33191E-02, -1.70910E-02 5.54302E+02, 4.81357E-001, 4.75992E-001 1.01538E-01, 9.08377E-02, -9. 19324E-02 -9.93277E-03, 8.94698E-02, 8.29828E-03 8.86808E+00, -4.74779E+00, -4.92191E-01 -6.74775E-04, -4.16015E-03, 2.76833E-03 3.57104E-04, -1.45437E-03, 8.70530E-04 -2.91818E-04, -1. 71502E-03, -1. 70371E-03 2.87472E-04, 3.81244E-03, -5.70459E-03 5.96706E+02, 3.38649E+01, -1. 06304E+0 1 6.06875E-01, 8.52691E+00, -1.53784E+01 1.06405E+00, 7.52749E+00, -1.59711E+00 -1.46476E-04, 4.02165E-03, -2.18420E-03 1. 76000E-002, 2.70000E+01, 5.00000E+00 7.08322E-010, 7.08322E-010, 3.88315E-010 1.00000E+000, O.OOOOOE+OOO, O.OOOOOE+OOO 1.00000E+000, O.OOOOOE+OOO, O.OOOOOE+OOO 518 ApPENDIX A O.OOOOOE+OOO, O.OOOOOE+OOO, O.OOOOOE+OOO O.OOOOOE+OOO, O.OOOOOE+OOO, O.OOOOOE+OOO * Gate Oxide Thickness is 176 Angstroms *PMOS PARAMETERS -3.13668E-Ol, 7.71734E-02, -8.49659E-02 7.46549E-Ol, O.OOOOOE+OO, O.OOOOOE+OO 4.90935E-Ol, -1.06839E-Ol, 1.39901E-Ol -8.01381E-03, 4.93369E-03, 2.51322E-02 -1.17312E-02, 2.85411E-02, -1.52749E-03 1.78348E+02, 3.17007E-001, 4.86131E-001 1.57383E-Ol, 9.28071E-02, -9.12893E-02 -5.32992E-03, 4.19297E-02, 1.02423E-02 8.400 17E+00, -2.31231E+00, -3.92977E-Ol -1.