Low-power Volatile and Non-volatile Memory Design by Qing Dong A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of Michigan 2017 Doctoral Committee: Professor Dennis Michael Sylvester, Chair Professor David Blaauw Professor Branko Kerkez Professor Zhengya Zhang Qing Dong [email protected] ORCID ID: 0000-0002-1380-269X © Qing Dong 2017 i DEDICATION To my family & friends… This dissertation is dedicated to my family and friends that supported, encouraged, and inspired me throughout my education. ii Table of Contents DEDICATION............................................................................................................................... ii LIST OF FIGURES ..................................................................................................................... vi LIST OF TABLES ..................................................................................................................... xiii ABSTRACT ................................................................................................................................ xiv CHAPTER 1. Introduction ......................................................................................................... 1 1.1 Low-power SRAMs and In-memory-computing ............................................... 4 1.2 NOR Flash Memory .............................................................................................. 6 1.3 STT-MRAM Memory ........................................................................................... 7 1.4 Emerging Spintronic Devices ............................................................................... 8 1.5 Thesis Organization .............................................................................................. 8 CHAPTER 2. Low-power 5T SRAM ....................................................................................... 11 2.1 Introduction ......................................................................................................... 11 2.2 Bitcell Design and Decoupled Read ................................................................... 12 2.3 Write Operation .................................................................................................. 15 2.4 Results .................................................................................................................. 20 2.5 Conclusion ........................................................................................................... 22 CHAPTER 3. 4+2T SRAM for Searching and in-memory-computing Applications .......... 23 3.1 Introduction ......................................................................................................... 23 iii 3.2 4+2T SRAM Cell Design .................................................................................... 24 3.3 Write Operation .................................................................................................. 25 3.4 Read Operation and Logic-in-memory Operation .......................................... 26 3.5 BCAM/TCAM Search Operation ...................................................................... 27 3.6 Results .................................................................................................................. 29 3.7 Conclusion ........................................................................................................... 33 CHAPTER 4. Low-power NOR Flash ..................................................................................... 34 4.1 Introduction ......................................................................................................... 34 4.2 High Voltage Generation .................................................................................... 35 4.3 High Voltage Delivery......................................................................................... 39 4.4 Low Power Voltage Reference & Current Reference ..................................... 41 4.5 Array Organization ............................................................................................ 56 4.6 Sense Amplifier Design ....................................................................................... 56 4.7 Results .................................................................................................................. 59 4.8 Conclusion ........................................................................................................... 63 CHAPTER 5. STT-MRAM Design .......................................................................................... 64 5.1 STT-MRAM Concept ......................................................................................... 64 5.2 Proposed Read Assist .......................................................................................... 65 5.3 Proposed Write Assist......................................................................................... 67 5.4 Results .................................................................................................................. 68 5.5 Conclusion ........................................................................................................... 71 iv CHAPTER 6. Racetrack Converter for High-speed Imaging System .................................. 72 6.1 Introduction ......................................................................................................... 72 6.2 Racetrack Memory Device ................................................................................. 73 6.3 Propose Racetrack Converter ............................................................................ 76 6.4 Uncertainty Analysis ........................................................................................... 84 6.5 Simulation Results and Analysis ....................................................................... 86 6.6 High-Speed Image Sensor with Racetrack ADCs ............................................ 91 6.7 Conclusion ........................................................................................................... 94 CHAPTER 7. Neural Network with Spintronic Devices ........................................................ 95 7.1 Introduction ......................................................................................................... 95 7.2 Components of Spin Neural Network ............................................................... 96 7.3 Neuron Network Architecture ......................................................................... 100 7.4 Simulation Results and Analysis ..................................................................... 107 7.5 Conclusion ......................................................................................................... 112 CHAPTER 8. Conclusion ........................................................................................................ 113 8.1 Contributions of This Work ............................................................................. 113 8.2 Future Directions .............................................................................................. 114 8.3 Related Publications ......................................................................................... 116 BIBLIOGRAPHY ..................................................................................................................... 118 v LIST OF FIGURES Figure 1.1 SRAM bitcell technology scaling and VDDmin scaling .............................................. 1 Figure 1.2 Intel processor with >50% of area for cache ................................................................. 2 Figure 1.3 Comparison between conventional method and in-memory computing ....................... 5 Figure 1.4 Spit-gate NOR Flash Cell .............................................................................................. 6 Figure 1.5 Battery-powered mm-scale sensor node systems ........................................................ 7 Figure 1.6 Magnetic tunnel junction cell ...................................................................................... 8 Figure 2.1 Architecture of the face detection and recognition processor ................................ 11 Figure 2.2 Proposed 5T memory bit cell design. VDDL/VDDR and VSSL/VSSR are the left/right power and ground terminals, respectively ............................................... 12 Figure 2.3 Layout of 5T bit cell. Isolated read and write paths allow for minimum-sized pull-up and pull-down devices ................................................................................. 13 Figure 2.4 Readout path of 5T memory. .................................................................................... 14 Figure 2.5 Basic write operation of 5T memory. VDDL is the lowered voltage level of VDD and VSSH is the raised voltage level of VSS. ......................................................... 15 Figure 2.6 Example of write disturbance issue. Writing into Cell_00 also affects other bit cells including Cell_10.............................................................................................. 16 Figure 2.7 Memory reset scheme ............................................................................................... 16 Figure 2.8 Sequential write scheme. .......................................................................................... 17 Figure 2.9 Initial write margins of 5T memory design. VDD moves from