Intel® Itanium® Processor 9300 Series, 9500 Series and 9700 Series Intel® Itanium® Processor Quad-Core 1.86-1.73 GHz with 24 MB L3 Cache 9350 Intel® Itanium® Processor Quad-Core 1.73-1.60 GHz with 20 MB L3 Cache 9340 Intel® Itanium® Processor Quad-Core 1.60-1.46 GHz with 20 MB L3 Cache 9330 Intel® Itanium® Processor Quad-Core 1.46-1.33 GHz with 16 MB L3 Cache 9320 Intel® Itanium® Processor Dual-Core 1.60 GHz Fixed Frequency with 10 MB L3 Cache 9310 Intel® Itanium® Processor Eight-Core 2.53 GHz with 32 MB LLC Cache 9560 Intel® Itanium® Processor Four-Core 2.40 GHz with 32 MB LLC Cache 9550 Intel® Itanium® Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9540 Intel® Itanium® Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9520 Intel® Itanium® Processor Eight-Core 2.66 GHz with 32 MB LLC Cache 9760 Intel® Itanium® Processor Four-Core 2.53 GHz with 32 MB LLC Cache 9750 Intel® Itanium® Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9740 Intel® Itanium® Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9720 Datasheet May 2017 Reference Number: 322821-003 ® ® 2 Intel Itanium Processor 9300, 9500, and 9700 Series Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. 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The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm%20 I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American Phillips Corporation. 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All Rights Reserved. ® ® Intel Itanium Processor 9300, 9500, and 9700 Series Datasheet 3 Contents 1 Introduction ........................................................................................................... 11 1.1 Overview ......................................................................................................... 11 1.2 Architectural Overview ...................................................................................... 19 1.2.1 Intel® Itanium® Processor 9300 Series Overview....................................... 19 1.2.2 Intel® Itanium® Processor 9500 Series Overview....................................... 20 1.2.3 Intel® Itanium® Processor 9700 Series Overview....................................... 23 1.3 Processor Feature Comparison............................................................................ 23 1.4 Processor Abstraction Layer ............................................................................... 24 1.5 Mixing Processors of Different Frequencies and Cache Sizes.................................... 24 1.6 Terminology..................................................................................................... 24 1.7 State of Data ................................................................................................... 25 1.8 Reference Documents........................................................................................ 25 2 Electrical Specifications .......................................................................................... 27 2.1 Intel® QuickPath Interconnect and Intel® Scalable Memory Interconnect Differential Signaling..........................................................................................27 2.2 Signal Groups................................................................................................... 28 2.3 Reference Clocking Specifications........................................................................ 30 2.4 Intel® QuickPath Interconnect and Intel® SMI Signaling Specifications..................... 32 2.4.1 Intel® Itanium® Processor 9300 Series Intel® QuickPath Interconnect and Intel® SMI Specifications for 4.8 GT/s32 2.4.2 Intel® Itanium® Processor 9500 and 9700 Series Requirements for Intel® QuickPath Interconnect for 4.8 and 6.4 GT/s36 2.4.3 Intel® Itanium® Processor 9500 Series Processor Requirements for Intel® SMI Specifications for 6.4 GT/s41 2.5 Processor Absolute Maximum Ratings .................................................................. 42 2.5.1 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings .............. 43 2.5.2 Intel® Itanium® Processor 9500 and 9700 Series Absolute Maximum Ratings 43 2.6 Processor DC Specifications................................................................................ 43 2.6.1 Flexible Motherboard Guidelines for the Intel® Itanium® Processor 9300 Series . 44 2.6.2 Flexible Motherboard Guidelines for the Intel® Itanium® Processor 9500 and 9700 Series 47 2.6.3 Intel® Itanium® Processor 9300 Series Uncore, Core, and Cache Tolerances . 49 2.6.4 Intel® Itanium® Processor 9500 and 9700 Series Uncore and Core Tolerances.. 53 2.6.5 Overshoot and Undershoot Guidelines....................................................... 57 2.6.6 Signal DC Specifications.......................................................................... 58 2.6.7 Motherboard-Socket Specification for VR Sense Point.................................. 62 2.7 Core and Uncore Voltage Identification ................................................................ 62 2.7.1 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9300 Series63 2.7.2 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9500 and 9700 Series 64 2.8 Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only)............... 67 2.9 RSVD, Unused, and DEBUG Pins ......................................................................... 68 2.10 Mixing Processors ............................................................................................. 69 2.11 Supported Power-up Voltage Sequence................................................................ 69 2.11.1 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9300 Series71 2.11.2 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9500 and 9700 Series 72 2.11.3 Power-up Voltage Sequence Timing Requirements...................................... 73 2.12 Supported Power-down Voltage Sequence............................................................ 73 ® ® 4 Intel Itanium Processor 9300, 9500, and 9700 Series Datasheet 2.13 Timing Relationship Between RESET_N and SKTID ................................................. 74 2.14 Test Access Port (TAP) Connection....................................................................... 76 3 Pin Listing ............................................................................................................... 77 3.1 Processor Package Bottom Pin Assignments .........................................................
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