6.012 - Microelectronic Devices and Circuits Lecture 17 - Linear Amplifier Basics; Biasing - Outline • Announcements Announcements - Stellar postings on linear amplifiers Design Problem - Will be coming out next week, mid-week. • Review - Linear equivalent circuits LECs: the same for npn and pnp; the same for n-MOS and p-MOS; all parameters depend on bias; maintaining a stable bias is critical • Biasing transistors Current source biasing Transistors as current sources Current mirror current sources and sinks • The mid-band concept Dealing with charge stores and coupling capacitors • Linear amplifiers Performance metrics: gains (voltage, current, power) input and output resistances power dissipation bandwidth Multi-stage amplifiers and two-port analysis Clif Fonstad, 11/10/09 Lecture 17 - Slide 1 The large signal models: A qAB q : Excess carriers on p-side plus p-n diode: IBS AB excess carriers on n-side plus junction depletion charge. B qBC C BJT: npn q : Excess carriers in base plus E- !FiB’ BE (in F.A.R.) iB’ B junction depletion charge B qBC: C-B junction depletion charge IBS qBE E D q : Gate charge; a function of v , MOSFET: qDB G GS qG v , and v . n-channel DS BS iD qDB: D-B junction depletion charge G B qSB: S-B junction depletion charge S qSB Clif Fonstad, 11/10/09 Lecture 17 - Slide 2 Reviewing our LECs: Important points made in Lec. 13 We found LECs for BJTs and MOSFETs in both strong inversion and sub-threshold. When vbs = 0, they all look very similar: in iin Cm iout out + + v in gi gmv in go v out C C - i o - common common Most linear circuits are designed to operate at frequencies where the capacitors look like open circuits. We can thus do our designs neglecting them.* Bias dependences: BJT ST MOS SI MOS gi : qIC "F kT 0 0 gm : qIC kT qID n kT 2KID # ST = sub-threshold SI = strong inversion go : $ IC $ ID $ ID The LEC elements all depend on the bias levels. Establishing a known, stable bias point is a key part of linear circuit design. We use our large signal models in this design and analysis. ! * Only when we want to determine the maximum frequency to which Clif Fonstad, 11/10/09 Lecture 17 - Slide 3 our designs can usefully operate must we include the capacitors. LECs: Identifying the incremental parameters in the characteristics MOSFET: iD (iD)1/2 Inc. |v | gm BS Q Q go ! Inc. vGS vDS VT vGS = vDS gm = diD/dvGS|Q; gmb = ηgm with η = -dVT/dvBS|Q; go = diD/dvDS|Q iC ln iB, ln iC BJT: iC Q IC iB ! ! IC go Q Inc. iB vCE vCE gm = qIC/kT; gπ = βgm with β = diC/diB|Q; go = diC/dvCE|Q Clif Fonstad, 11/10/09 Lecture 17 - Slide 4 Linear equivalent circuits for transistors (dynamic): Collecting our results for the MOSFET and BJT biased in FAR MOSFET: Cgd g = K V "V (V ) 1+ #V $ 2K I g d m [ GS T BS ][ DS ] D + K 2 ID v gs go = [VGS "VT (VBS )] # $ # ID = gmv gs gmbv bs go 2 V Cgs A s - s - gmb = % gm = % 2K ID v bs Cdb 'VT 1 (SiqNA Csb Cgb with + % & " = * b 'vBS Q Cox q) p "VBS 2 C = W LC* , C ,C ,C : depletion capacitances gs 3 ox sb gb db * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic) ! q qVBE kT qIC BJT: gm = "oIBS e [1+ #VCE ] $ kT kT ! Cµ b c gm qIC + g% = = "o "o kT g! v ! gmv ! go C! I - qVBE kT C e e go = "oIBS [e +1] # $ # IC = VA w 2 C = g # + B-E depletion cap. with # $ B , C : B-C depletion cap. " m b b 2D µ Clif Fonstad, 11/10/09 e Lecture 17 - Slide 5 ! ! MOSFETs and BJTs biased for use in linear amplifiers +V +V +V +V IBIAS IBIAS IBIAS IBIAS -V -V -V -V n-MOS p-MOS npn pnp Clif Fonstad, 11/10/09 Lecture 17 - Slide 6 * Getting IBIAS: Making a transistor into a current source/sink ISINK ISINK + + VREF VREF - - + + VREF VREF - - ISOURCE ISOURCE npn pnp n-MOS p-MOS BJT current sources/sinks MOSFET current sources/sinks Must maintain VCE > 0.2V Must maintain VDS > (VREF - VT) [VEC in case of pnp] [VSD > (VREF + VT) in case of p-MOS] qVREF/kT 2 ISOURCE/SINK = [βF/(βF+1)] IES(e -1) ISOURCE/SINK = K(VREF - |VT|) /2 qVREF/kT ≈ IESe * Some people make a distinction between a "sink" and a Clif Fonstad, 11/10/09 "source"; you can call them all "sources" if you wish. Lecture 17 - Slide 7 Getting IBIAS: Setting VREF for a current source/sink V+ V+ V+ Circuit Circuit Circuit being being RG1 being biased biased biased ISINK ISINK ISINK QA QA + + VREF - RG2 V- V- VREF Concept MOSFET version - V- Simple resistor divider: too sensitive to device to device variations of VT, K Clif Fonstad, 11/10/09 Lecture 17 - Slide 8 Getting IBIAS: Setting VREF, cont. V+ V+ V+ Circuit Circuit Circuit being being being RG1 RG1 biased biased biased ISINK ISINK ISINK Q QA QB QA + A + + V V REF - REF - V- RG2 RS VREF - MOSFET version V- V- Divider with RG: less Current Mirror: matches VT, sensitive to variations in K variations; easy to bias VT, K, but not perfect; multiple stages; only 1 R* Clif Fonstad, 11/10/09 resistors are undesirable Lecture 17 - Slide 9 * We'll see how to make this zero.. Current mirror sources/sinks: establishing VREF; setting I V+ V+ MOSFET + ISINKRREF = 1/2 VREF mirrors RREF (KQ2/KQ1)[V+ -V - -V T - (2ISINK/KQ1) ] - Q1 Q 2 ISINK ISOURCE Q1 Q2 I R = + RREF SOURCE REF V (K /K )[V -V -V - (2I /K )1/2] REF Q2 Q1 + - T SOURCE Q1 - V- V- V+ V+ BJT + I R = (A /A )(V -V - 0.6) VREF mirrors RREF SINK REF Q2 Q1 + - - Q1 Q2 ISINK I SOURCE Q1 Q2 + I R = (A /A )(V -V - 0.6) RREF SOURCE REF Q2 Q1 + - VREF - V- NOTE: Base currents have not been V- Clif Fonstad, 11/10/09 accounted for in these expressions Lecture 17 - Slide 10 Examples of current mirror biased MOSFET circuits: V+ V+ V+ ID ID ID RREF RREF Q1 Q1 IREF IREF IBIAS Q Q Q Q -V 2 3 2 3 Above: Concept Right: Implementations V- V- MOSFET Mirror BJT Mirror ID ≈ (KQ3/KQ2) IREF ID ≈ (AQ3/AQ2) IREF Clif Fonstad, 11/10/09 Lecture 17 - Slide 11 Final comment on current sources: What do they look like incrementally? They look like a resistor with conductance go For example, consider an n-MOS sink: I g d d SINK + gmbv bs v gs = 0 gmv gs g g = 0 o o s - = 0 s s, b, g + - VREF v bs = 0 - V+ b + ISINK RREF How do you do better (smaller go)? The cascode connection: Q1 Q2 - check it out for yourself - we'll come back to the cascode in Lec. 22 Q3 Q4 Clif Fonstad, 11/10/09 V- Lecture 17 - Slide 12 Linear amplifier layouts: The practical ways of putting inputs to, and taking outputs from, transistors to form linear amplifiers +V +V There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take 2 2 an output, and two choices of what to do with the remaining 1 1 node (ground it or connect it 3 3 to something). Not all these choices work IBIAS IBIAS well, however. In fact only -V -V three do: Name Input Output Grounded Common source/emitter 1 2 3 Common gate/base 3 2 1 Common drain/collector 1 3 2 (Source/emitter follower) Source/emitter degeneration 1 2 none Clif Fonstad, 11/10/09 Lecture 17 - Slide 13 • Three MOSFET single-transistor amplifiers V+ V+ V+ + C C CO vin O O - + + + vout vout vout + - IBIAS - vin - CI - + V- IBIAS IBIAS vIN SOURCE FOLLOWER CE Input: gate - Output: source V- V- Common: drain Substrate: to source COMMON SOURCE COMMON GATE Input: gate Input: source; Output: drain Output: drain Common: gate Common: source Substrate: to ground Substrate: to source + + + + + vin + vout vin vout vout vin - - - - - - Clif Fonstad, 11/10/09 Lecture 17 - Slide 14 Mid-band: the frequency range of constant gain and phase V+ Common emitter example: The linear equivalent circuit for the common emitter amplifier stage on the left is drawn below with all of the elements included: CO + C C v µ O + out v - + + + in rt - g! v in v ! gmv ! go IBIAS + C! g C v t - v out next E - gLOAD V- r IBIAS CE - - The capacitors are of two types: Biasing capacitors: they are typically very large (in µF range) (CO, CE, etc.) they will be effective shorts above some ωLO Device capacitors: they are typically very small (in pF range) (Cπ, Cµ, etc.) they will be effective open circuits below some ωHI Clif Fonstad, 11/10/09 Lecture 17 - Slide 15 Mid-band, cont. At frequencies above some value (≡ ωLO) the biasing capacitors look like shorts: Cµ SC CO + + + rt g! v in v ! gmv ! go ω < ω + C! g LO v t - v out next - gLOAD r IBIAS CE SC - - At frequencies below some value (≡ ωHI) the device capacitors look like open circuits: OC Cµ CO + + + rt g v ! v gmv ! g ω < ωHI in ! o + OC C! g v t - v out next - gLOAD r IBIAS CE - - Clif Fonstad, 11/10/09 Lecture 17 - Slide 16 Mid-band, cont.