System/370 Model 145 Reference Summary S229-2239-1 IBM Corporation, Field Support Documentation, Dept 927, Rochester, Minnesota 55901 PREFACE This publication is primarily intended for customer engineers servicing System/370 Model 145. Second Edition (September 1972) This is a major revision of, and makes 8229-2239-0 obsolete. Address any comments concerning the contents of this publication to: IBM, Field Support Documentation, Dept 927, Rochester, Minnesota 55901 © International Business Machines Corporation 1972 CONTENTS Section 1 - Control Words Branch and Module Switch Word "O" . 1. 1 Branch Word . 1.2 GA Function Charts . 1.3 GA Function Charts . 1.4 GA Function Charts . 1.5 Branch and Link or Return Word . 1.6 Word Move Word Version"O" . 1. 7 Word Move Word Version "1" . 1.8 Storage Word, Non K-Addressable . 1.9 Storage Word, K-Addressable . 1.10 Arithmetic Word 10 Byte Version 1.11 Arithmetic Word, Fullword Version 1.12 Arithmetic Word, 11 Direct ByteVersion . 1.13 Arithmetic Word, 10/11 Indirect Byte Version . 1.14 ALU Entry Gating 1.15 Stat Set Symbols . 1.15 BranchSymbols . 1.15 Arithmetic Word Chart Selection 1.16 Address Formation Chart 1.16 Control Word Chart Selection 1.16 Section 2 - CPU 3145 CPU Data Flow . 2.1 I-Cycles Data Flow . 2.2 I-Cycles . 2.3 PSW Locations . 2.3 Expanded Local Storage . 2.3 I-Cycles . 2.3 I-Cycles Control Line Generation . 2.4 Control Word . 2.4 Control Register Decode . 2.4 iii ECCL Board Layout ............ 2.5 Data Bit Location Chart .......... 2.5 Common Test Points ............ 2.6 3145 CPU BSM Addressing ......... 2.6 Main Storage Frame - 128K ........ 2.6 3345 Main Storage Frame - 256K ..... 2.6 CPU SAR Bits 15, 16, and 17 ....... 2.6 Memory Troubleshooting Procedure ... 2.7 Example Chart for Array Card Outputs of Phase 21 Memory .... 2.8 Cycle Length ................ 2.9 Local Storage Timing Chart . 2.10 External Destination Timing Chart . 2.11 Gate Layouts . 2.13 CPU Clock Information ......... 2.14 Trap Locations and Routines . 2.15 Feature Code Listing . 2.17 Feature Code Listing . 2.18 Feature Code Listing . 2.19 Feature Code Listing . 2.20 370 Coreload Feature Part Numbers .. 2.21 370 Coreload Feature Part Numbers . 2.22 ALO Page Index ............. 2.23 ALO Page Index ............. 2.24 ALO Page Index ............. 2.25 ALO Page Index ............. 2.26 ALO Page Index . 2.27 ALO Page Index . 2.28 ALO Page Index ............. 2.29 ALO Page Index . 2.30 Console Indicators - Logic Reference . 2.31 Upper Roller - Logic Reference 2.32 Lower Roller - Logic Reference . 2.33 Section 3 - Console File (23FD) Console File Control and Data Flow ... 3.1 iv Compare Mode . 3.2 Control Commands . 3.2 Operation Commands . 3.2 Console File Disk Address (CFDA) Byte 3.2 Console File Control Functions 3.3 CF Error Checks . 3.4 Byte Format . 3.5 Section 4 - Channels MPX Channel Data Flow 4.1 UCW Addressing Table . 4.2 Byte MPX UCW . 4.2 Selector Channel Data Flow 4.3 Standard Device Addresses . 4.4 Word Buffer . 4.4 Block Multiplex Feature . 4.5 UCW Pool . 4.6 UCW Assignment Registers . 4.6 UCW Format . 4.6 Section 5 - Integrated File Adapter (IFA) IFA Data Flow . 5.1 General Status Indications 5.2 I FA In-Line Tests . 5.2 IFA Information. 5.3 I FA Sense Information . 5.3 Control Words Forced for I FA Share Cycles . 5.4 IFA Local Storage Assignments 5.5 IFA CS Area . 5.5 I FA Drive Interface . 5.7 I FA Latches Logic References . 5.8 Section 6 - Console Printers 3210 Control and Data Flow 6.1 3215 Control and Data Flow 6.2 Alter/Display Functions 6.3 v Console Printer Valid Addresses ..... 6.4 Section 7 - Features Addr Adj Clock Comparitor, CPU Timer PSW Format . 7.1 Address Translate Process Overview . 7.2 Address Translate Process . 7.3 Address Translate Process . 7.4 Clock Comparitor CPU Timer (CPT) . 7.6 Section 8 - Software and Logouts System/370 Instructions Set . 8.1 Information Retrieval Under DOS/360 . 8.2 Control Registers . 8.4 CPU Independent Logout . 8.5 Machine Check Interrupt Code . 8.6 Model 145 Machine Dependent Log . 8. 7 1/0 Communications Area . 8.9 I FA Extended Logout . 8.10 MPX Channel Machine Dependent Log 8.10 Selector Channel/Block Multiplex Channel Dependent Log 8. 10 ECC Recording 8.11 ECC Recording 8.12 Section 9 - Power Power Supplies . 9.2 Power Reference Manual . 9.3 Relay Function and Location Chart . 9.4 Initial Regulator Adjustment for Power-Up Procedure . 9.5 Power-On Sequence . 9.6 Start Line Tips . 9.10 System Checklist . 9.10 Voltage Levels - Scoping Information 9.13 Miscellaneous Part Numbers . 9. 16 Section 10- Micro Diagnostics Basic Diagnostic FLT. ......10.1 vi Basic Diagnostic Information .. 10.2 Diagnostic Functions ..... 10.3 Local Storage Map (Diagnostic) . 10.4 Diagnostic Test Listing .. 10.5 Section 11 - Maps External Assignment Chart 11. 1 External Address Line Decoding 11.2 External Gating to A-Registers 11.2 FAT· Diagnostic Usage .11.27 Expanded Local Storage Map .11.30 Local Storage . .11.31 Local Storage . .11.32 Control Registers Bit Definitions .11.33 Direct Addressable Control Storage Map ............... .11.36 vii INDEX Section 1 - Control Words ................. II Section 2 - CPU ......................... E Section 3 - Console File .................. II Section 4 - Channels . ................. II Section 5 - I FA ........................ B Section 6 - Console Printer ................ m Section 7 - Features, Address Adjust, Clocks ... & Section 8 - Software and Logout ........... II Section 9 - Power and MST General ........ a Section 10 - Diagnostics ................. m Section 11 - MAPs ...................... Ill ix co Cl CJ o I ti ' I 3 • I s I • I ' o I 1 I ' I ' I • I s • l_1 o_l_1_1_7j_J "I• I s_l_•J_7 o 11 l'_l 3 '-151•1• 8ronc:h Sou~e 8tonc"o11d 81oncl. ln:i"(" Module: Sw1tc.h H1.,h Sov•te Module Ne,.1 A.ddr .. u Brol\C.f. low Wood ..... o... DODO 0 0 0 0 0 SH LS/(XT 0 0 I. Addi. Fo1rm 0001 I 1 s-a 1 ; 0010 ' 1-1 70 0011 "so J l·B NZ 0100 SJ 0101 " SS 0110 "S6 :.. 0111 SH "Bl 1000 BO .. 1001 .. 11 1010 B2 B2 1011 13 13 1100 •• .. 1101 11$ 15 1110 •• 16 1111 17 17 • II co Cl C2 CJ oj 1J2J J •Jsj .J 1 oj 1J 2J Jj •J s •J 7 0 I 2J J •JsJ•J' oJ1j2jJ •Jsl•l1 Btonch Source ' r. SIR 8l'Onch 8'on<h 6'onch High S/R K Neid Address HI-LO ~m~e low Wonl "''• 0 s.. LS/EXT 0 MS OR 0 Addr, Fo.- _; 0 0 0 I I I l Dk A-, '=~~s I -.u.o SI 2 H p zo ... _ajll 50 J ST GA NZ QIOO S2 SJ QIOI S• SS 16 57 _tll SH Bl 1000 BO 80 1001 81 Bl 1010 82 82 1011 BJ BJ 1100 .. .. 1101 BS BS 1110 116 116 1111 _LLl _l ~ _l _l _l _l _l_ _l _l _l _l _l _l _l _l _l _l I I B7 I Not•: When K Hl-LO=OO, no Mt/reset occurs, and C2 11 vied OI rhe module portion of the oddreu, which.•• tel 1nlo M2 (N2) i:== ......... Aho, du•1ng module 1Wttch1ng, T qg11lef bib 0 and I replace th. two 1--ord.r bib (C3,12-J) in 1ett1ng Ml(NJ),12-3 The bronch 10Urce field con odd,.. "'9 A lcx;ol 1tore on on When DK (C2 bit O=I) 11 on, the 01ag,_t1c Ke)" will •temol r91•tler. The bronch-t0urce b,te 11 Mt onto the A-reg bt 1et 1f the OI funct1°" •• ••gnoted, oncl •••• ,f th. A-functton •I deugnoted h Set GAL Reset GAL Set GAH Reset GAH (KFieldl GA, OR, KOh GA, A·, KOh GA, OR, KhO GA, A·, KhO 1 Set Poll Control (Soft) Reset Poll Control Set Channel 1 Channel Reset 2 Set Poll Control (Hdwr) Reset Retry Holdup Set Channel 2 Chain Reset 3 Set Command Retry Set Channel 3 Machine Reset 4 Set Channel 4 5 Set Count Ready Start I/0 Reset Set Channel Loaded Reset Channel Loaded 6 Set Protect Check Set Control Check Set CC Diag Buffer Shift ... 7 Set Program Check WLR Sample Set PCI Reset Interrupts w 8 Set Interrupt Latch Set DCC Mode Diag Block Share Req Reset DCC Mode and Diag Block Share Req 9 Set Select Out Reset Sel Out and Set Diag Stat Reset Diag Stat and Primed Interrupt Latch A Set Sup Out Reset Sup Out •set Channel Primed Set Channel Tried B Bus-In to GR •set Data Out c Set Op Out Reset Op Out and •set Command Out Set Addr Out Diag Set GR Full D Interface Control Check Diag Serv Signal •set Service Out Reset PCI E Set Diag Mode Reset Diag Mode •set Halt 1/0 Reset Halt 1/0 F *Also Set Retry Holdup Iii en C> h Set GAL Reset GAL Set GAH Reset GAH ~)> ::0 'Tl K Field GA, OR, KOh GA, A-, KOh GA, OR, KhO GA, A-. KhO lil c: 1 Set Increment Length Reset FCS Set IF A Channel Gate Reset Command ~z Reset PCI ("') (") 2 Set Prog Check Set Channel 2 Gate Overrun 0 -I 3 Set Prot Check Reset Trap Req Set Channel 3 Gate Machine Reset ::J - ~o 4 Set Channel Control Check Reset CCWO and Reset Orientation 2. z Cl> 5 Set Allow Restart WLR Set Write Clock Gate Latch (") Reset Lo Prior Req Q J: )> 6 Chain End Reset Reset Count Ready, Set CS,CR,ln Latches "Tl l:J 7 Set Contingent Con Reset Contingent1 Set CS,CR ,Out Latches In.Out l> -I 8 Set Allow IDA Con Set MS,CR,ln Latches Set Halt 1/0 (/) 9 Set Channel Busy Reset Channel Busy Set MS,CR,Out Latches CE End Op SS A Set Interrupt Latch Reset Interrupt Latch Set Control Pulse Diag Index D1ag Raw Data Pulse B Set CUB Reset CUB Diag Read Data Set D1ag Read Gate c Set DCC Reset DCC Diag Clock Gap Sense B 1t Ring Advance D Set Low Prior Req Rst H/L Comp,CC Er Diag Data Gap Sense Set Diag Mode Latch E Set IFA Inhibit Traps Rst IFA lnh Traps Set Data Field Latch Reset Diag Mode F Latch GA FUNCTION CHARTS HH Set GA Straight Reset GA Straight GA or KHH 11 Set Diag Block Share Not Used Cycle - All Channels • 22 Reset Diag Block Share Cycle Latch· All Not Used Channels Reset Blk MPX UCW Latch 33 Diag Check Reset Not Used All Channels 44 Set Diagnostic Function Latch and Diag Reset Not Used Exp LIS Reset UCW Scan Latch 66 All Channels Not Used Allow Trap Latch Set/Reset Set UCW Scan Latch 88 All Channels Block Trap Latch Set/Reset FF Reset Diagnostic Not Used Function Latch 1.5 co Cl C2 CJ • :E ttl 0 l:J o_L 1_12 I , • s 1•J7 0J1j2J3j •l>_l• 17 01112131•1>1•17 o__L 1_12_13 • >_1•_17 .