Modicon Ladder Logic Block Library User Guide 840 USE 101 00 Version 3.0 August 2001 Schneider Electric One High Street North Andover , MA 01845 Preface The data and illustrations found in this book are not binding. We reserve the right to modify our products in line with our policy of continuous product development. The information in this document is subject to change without notice and should not be construed as a commitment by Schneider Electric. Schneider Electri c assumes no responsibility for any errors that may appear in this document. If you have any suggestions for improvements or amendments or have found errors in this publication, please notify us by using the form on the last page of this publication. No part of this document may be reproduced in any form or by any means, electronic or mechanical, including photocopying, without express written permission of the Publisher, Schneider Electric. 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Copyright 20 01, Schneider Electric Printed in U.S.A. 840 USE 101 00 Preface iii Contents Chapter 1 Ladder Logic Overview........................... 1 1.1 Segments and Networks in Ladder Logic......................... 2 1.1.1 A Ladder Logic Network............................. 2 1.1.2 Coil Placement in a Network......................... 3 1.1.3 Ladder Logic Segments.............................. 4 1.2 How a PLC Solves Ladder Logic................................. 5 1.3 Ladder Logic Elements and Instructions.......................... 7 Chapter 2 Memory Allocation in a PLC....................... 11 2.1 User Memory.................................................. 12 2.1.1 User Logic.......................................... 12 2.1.2 User Memory....................................... 12 2.1.3 System Overhead................................... 13 2.1.4 Memory Backup.................................... 13 2.2 State RAM Values.............................................. 14 2.2.1 A Referencing System for Inputs and Outputs......... 14 2.2.2 Storing Discrete and Register Data in State RAM...... 15 2.3 State RAM Structure........................................... 16 2.3.1 Minimum Required State RAM Values................ 17 2.3.2 History and Disable Bits for Discrete References....... 17 2.4 The Configuration Table........................................ 18 2.4.1 Assigning a Battery Coil............................. 18 2.4.2 Assigning a Timer Register.......................... 18 2.4.3 The Time of Day Clock............................... 19 2.4.4 Configuration Overview............................. 20 2.5 The I/O Map Table.............................................. 22 2.5.1 Determining the Size of the I/O Map Table............. 22 2.5.2 Writing Data to the I/O Map Table.................... 22 840 USE 101 00 Contents v Chapter 3 Ladder Logic Opcodes........................... 23 3.1 Translating Ladder Logic Elements in System Memory............ 24 3.1.1 Translating Logic Elements and Non-DX Functions.... 24 3.2 Translating DX Instructions in the System Memory Database...... 26 3.2.1 How the x and z Bits Are Used in 16-bit Nodes......... 26 3.2.2 How the x and z Bits Are Used in 24-bit Nodes......... 27 3.2.3 Opcodes for Standard DX Instructions................ 28 3.2.4 How the y Bits are Utilized for DX Functions.......... 28 3.3 Opcode Defaults for Loadables................................... 29 3.3.1 How to Handle Opcode Conflicts...................... 29 Chapter 4 Ladder Logic Elements........................... 31 4.1 Contacts....................................................... 32 4.1.1 Normally Open Contacts............................. 32 4.1.2 Normally Closed Contacts............................ 33 4.1.3 Positive Transitional Contacts........................ 33 4.1.4 Negative Transitional Contacts....................... 34 4.2 Coils.......................................................... 36 4.2.1 Normal Coils....................................... 36 4.2.2 Latched or Memory-retentive Coils................... 36 4.2.3 A Simple Contact-Coil logic Example.................. 37 4.2.4 Coil Usage in a Logic Network........................ 37 4.2.5 General Coil Usage Guidelines....................... 38 4.3 Shorts......................................................... 39 4.3.1 Horizontal Shorts................................... 39 4.3.2 Vertical Shorts...................................... 39 4.4 Using Logic Elements to Create Control Circuits.................. 40 4.4.1 A Logical AND Circuit............................... 40 4.4.2 A Logical OR Circuit................................ 40 4.4.3 A Logical XOR Circuit............................... 41 4.4.4 Building a Seal Circuit.............................. 41 4.5 Storing Contacts and Coils in Registers........................... 43 4.6 NOBT......................................................... 45 4.7 NCBT......................................................... 47 4.8 NBIT.......................................................... 49 4.9 SBIT.......................................................... 51 4.10 RBIT.......................................................... 53 vi Contents 840 USE 101 00 4.11 Example: Implementing a Motor Starter Circuit................... 55 Chapter 5 Counters and Timers............................. 59 5.1 UCTR......................................................... 60 5.1.1 Characteristics...................................... 60 5.1.2 Representation in Ladder Logic....................... 60 5.1.3 Up-Counter Example................................ 61 5.2 DCTR......................................................... 62 5.3 T1.0 Timer..................................................... 64 5.3.1 Characteristics...................................... 64 5.3.2 Representation in Ladder Logic....................... 64 5.3.3 A One-second Timer Example........................ 66 5.4 T0.1 Timer..................................................... 67 5.5 T.01 Timer..................................................... 69 5.6 T1MS Timer................................................... 71 5.6.1 Characteristics...................................... 71 5.6.2 Representation in Ladder Logic....................... 71 5.6.3 A Millisecond Timer Example........................ 72 Chapter 6 Integer and 16-bit Math Instructions............... 75 6.1 ADD.......................................................... 76 6.2 SUB.......................................................... 78 6.3 MUL.......................................................... 80 6.4 DIV........................................................... 82 6.5 AD16.......................................................... 84 6.6 SU16.......................................................... 86 6.7 TEST......................................................... 88 6.8 MU16......................................................... 90 6.9 DV16.......................................................... 93 6.10 ITOF.......................................................... 96 6.11 FTOI.......................................................... 98 6.12 BCD.......................................................... 100 6.13 A Fahrenheit-to-Centigrade Conversion Example.................. 102 Chapter 7 Enhanced Math Capabilities...................... 103 7.1 Capabilities of the EMTH Instruction............................ 104 840 USE 101 00 Contents vii 7.2 Double Precision EMTH Functions............................... 107 7.2.1 Double Precision Addition............................ 107 7.2.2 Double Precision Subtraction......................... 108 7.2.3 Double Precision Multiplication...................... 109 7.2.4 Double Precision Division............................ 110 7.3 Integer EMTH Functions........................................ 111 7.3.1 Square Root........................................ 111 7.3.2 Process Square Root................................. 112 7.3.3 Base 10 Logarithm.................................. 114 7.3.4 Base 10 Antilogarithm............................... 115 7.4 Floating Point EMTH Functions................................. 116 7.4.1 The IEEE Floating Point Standard................... 116 7.4.2 Dealing with Negative Floating Point Numbers........ 116 7.4.3 Integer-to-Floating Point Conversion.................. 117 7.4.4 Integer + Floating Point Addition..................... 118 7.4.5 Integer Floating Point Subtraction.................. 118 7.4.6 Integer x Floating Point Multiplication................ 119 7.4.7 Integer Divided by Floating Point..................... 119 7.4.8 Floating Point Integer Subtraction.................. 120 7.4.9 Floating Point Divided by Integer..................... 120 7.4.10 Integer-Floating Point Comparison................... 121 7.4.11 Floating Point-to-Integer Conversion.................. 122 7.4.12 Floating Point Addition.............................