TRANSISTOR-LEVEL PROGRAMMABLE FABRIC by Jingxiang Tian APPROVED BY SUPERVISORY COMMITTEE: ___________________________________________ Carl Sechen, Chair ___________________________________________ Yiorgos Makris, Co-Chair ___________________________________________ Benjamin Carrion Schaefer ___________________________________________ William Swartz Copyright 2019 Jingxiang Tian All Rights Reserve TRANSISTOR-LEVEL PROGRAMMABLE FABRIC by JINGXIANG TIAN, BS DISSERTATION Presented to the Faculty of The University of Texas at Dallas in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT DALLAS December 2019 ACKNOWLEDGMENTS I would like to express my deep sense of gratitude to the consistent and dedicated support of my advisor, Dr. Carl Sechen, throughout my entire PhD study. You have been a great mentor, and your help in my research and career is beyond measure. I sincerely thank my co-advisor, Dr. Yiorgos Makris, who brings ideas and funds for this project. I am grateful that they made it possible for me to work on this amazing research topic that is of great interest to me. I would also like to thank my committee members, Dr. Benjamin Schaefer and Dr. William Swartz for serving as my committee members and giving lots of advice on my research. I would like to give my special thanks to the tech support staff, Steve Martindell, who patiently helped me a thousand times if not more. With the help of so many people, I have become who I am. My parents and my parents-in-law give me tremendous support. My husband, Tianshi Xie, always stands by my side when I am facing challenges. Ada, my precious little gift, is the motivation and faith for me to keep moving on. “I didn’t come this far to only come this far.” Graduation is not only the end of my student career, but also the starting point of more possibilities. I am looking forward to uncovering the future. October 2019 iv TRANSISTOR-LEVEL PROGRAMMABLE FABRIC Jingxiang Tian, PhD The University of Texas at Dallas, 2019 ABSTRACT Supervising Professor: Carl Sechen, Chair Yiorgos Makris, Co-Chair We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. This TRAnsistor-level Programmable (TRAP) fabric allows simultaneous storage of four independent configurations, along with the ability to dynamically switch between them in a small fraction of a clock cycle. We term this board-level virtualization in that each configuration, in effect, implements an independent chip. TRAP also supports chip-level virtualization in which a single IC design is partitioned over a set of configurations and the computation cycles from one configuration to the next in the set. This allows a design that requires more computational logic than physically available on the TRAP chip to be nonetheless executable. TRAP also features rapid partial or full modification of any one of the stored configurations in a time proportional to the number of modified configuration bits through the use of hierarchically arranged, high throughput, pipelined memory buffers. TRAP supports libraries of cells of the same height and variable width, just as in a typical standard cell circuit. We developed a complete Computer-aided Design (CAD) tool flow for programming TRAP chips. A prototype 3mm X 3mm TRAP chip was fabricated using the Global Foundries 55nm process. We v show that TRAP has substantially better area efficiency compared to a leading industrial FPGA and would, therefore, be ideal for embedded FPGA (eFPGA) applications. vi TABLE OF CONTENTS ACKNOWLEDGMENTS............................................................................................................. iv ABSTRACT .................................................................................................................................. v LIST OF FIGURES...................................................................................................................... xi LIST OF TABLES……............................................................................................................... xiv CHAPTER 1 INTRODUCTION............................................................................................... 1 1.1 Industrial Architectures ....................................................................................... 2 1.2 Novel Architectures in Research.......................................................................... 8 CHAPTER 2 TRAP OVERVIEW ...........................................................................................11 2.1 A Brief Introduction to TRAP ............................................................................11 2.2 TRAP Features and Applications ........................................................................12 2.2.1 Virtualization ..........................................................................................12 2.2.2 Rapid Selective Reprogramming .............................................................13 2.2.3 Seamless Transition with ASIC Flow ......................................................13 2.2.4 Mixed TRAP and ASIC Design ..............................................................14 CHAPTER 3 DESIGN DETAIL OF TRAP .............................................................................15 3.1 Logic Cell & Built-in Gates ................................................................................15 3.1.1 Logic Cell ...............................................................................................15 3.1.2 Built-in Gates ..........................................................................................19 3.1.3 Advantages .............................................................................................22 3.2 Board-level Virtualization and Chip-level Virtualization ....................................23 3.2.1 Board-level Virtualization .......................................................................23 3.2.2 Chip-level Virtualization .........................................................................24 vii 3.3 Interconnect Architecture ...................................................................................27 3.3.1 Switch .....................................................................................................27 3.3.2 Segment ..................................................................................................30 3.3.3 Challenge in Routing ..............................................................................32 3.3.4 Area Benefit and Structure Superiority ....................................................33 3.4 Local Memory Cell ............................................................................................33 3.4.1 Memory Cell Architecture .......................................................................33 3.4.2 Dynamic Reconfiguration .......................................................................35 3.5 Hierarchical Function Blocks .............................................................................37 3.5.1 Unit.........................................................................................................37 3.5.2 Group......................................................................................................38 3.6 Core Programming .............................................................................................39 3.6.1 Partial/Full Core Programming................................................................39 3.6.2 Hierarchical Bi-directional Memory Buffer .............................................40 3.6.3 Asynchronous Pipelined Control .............................................................44 3.7 I/O Design and Programming .............................................................................48 3.7.1 Power Pad Design ...................................................................................48 3.7.2 Digital I/O Pad and Bi-directional I/O Pad Design ..................................49 3.7.3 Metal Track Selecting Multiplexer ..........................................................53 3.7.4 I/O Programming ....................................................................................55 3.8 Clock Tree Design..............................................................................................62 3.9 Power Network Design.......................................................................................63 CHAPTER 4 DESIGN DECISIONS .......................................................................................66 4.1 Logic Cell Design Decisions ..............................................................................66 viii 4.2 Programmable Interconnect Design Decisions ....................................................67 4.3 Design of Virtualizations ....................................................................................71 4.4 Memory Design Decisions .................................................................................71 4.5 Core Programming Design Decisions .................................................................73 4.6 I/O Programming Design Decision .....................................................................73 CHAPTER 5 FABRICATION AND PACKAGE ....................................................................75 5.1 FPTA Design Layout..........................................................................................75