Special Session: Exploring the Ultimate Limits of Adiabatic Circuits Michael P. Frank Robert W. Brocato Thomas M. Conte Alexander H. Hsia Cognitive & Emerging RF Microsystems Dept. Schools of Computer Science and Sandia National Laboratories Computing Dept. Sandia National Laboratories Electrical & Computer Eng. Albuquerque, NM, USA Sandia National Laboratories Albuquerque, NM, USA Georgia Institute of Technology Albuquerque, NM, USA orcid:0000-0001-9751-1234 Atlanta, GA, USA Requiescat in pace [email protected] [email protected] Anirudh Jain Nancy A. Missert Karpur Shukla Brian D. Tierney School of Computer Science Nanoscale Sciences Department Laboratory for Emerging Radiation Hard CMOS Georgia Institute of Technology Sandia National Laboratories Technologies Technology Dept. Atlanta, GA, USA Albuquerque, NM, USA Brown University Sandia National Laboratories [email protected] orcid:0000-0003-2082-2282 Providence, RI, USA Albuquerque, NM, USA orcid:0000-0002-7775-6979 [email protected] Abstract—The field of adiabatic circuits is rooted in electronics I. INTRODUCTION know-how stretching all the way back to the 1960s and has poten- tial applications in vastly increasing the energy efficiency of far- In 1961, Rolf Landauer of IBM observed that there is a fun- future computing. But now, the field is experiencing an increased damental physical limit to the energy efficiency of logically ir- level of attention in part due to its potential to reduce the vulnera- reversible computational operations, meaning, those that lose bility of systems to side-channel attacks that exploit, e.g., unwan- known information to their thermal environment [1]. This ob- ted EM emissions, power supply fluctuations, and so forth. servation, now enshrined as Landauer’s Principle, is today un- In this context, one natural question is: Just how low can the derstood (with some important qualifications) as a rigorous the- energy dissipation from adiabatic circuits, and the associated ex- orem of fundamental statistical physics and information theory traneous signal emissions, be made to go? We argue that the ulti- [2], and is widely considered to be one of the most important mate limits of this approach lie much farther away than is com- results in the fundamental physics of computing. monly appreciated. Recent advances at Sandia National Labora- tories in the design of fully static, fully adiabatic CMOS logic styles During the 1970s, Landauer’s protégé Charles Bennett real- and high-quality energy-recovering resonant power-clock drivers ized that an alternative paradigm for computation based on log- offer the potential to reduce dynamic switching losses by multiple ically reversible operations, which could in principle sidestep orders of magnitude, and, particularly for cryogenic applications, Landauer’s efficiency limit, was theoretically coherent [3], and optimization of device structures can reduce the standby power developed a more sophisticated understanding of the thermody- consumption of inactive devices, and the ultimate dissipation li- namics of computation built on this insight [4], [5]. Early con- mits of the adiabatic approach, by multiple orders of magnitude cepts for engineering implementations of reversible computing as well. (e.g., [6], [7]) eventually led to Younis & Knight’s discovery (in In this paper, we review the above issues, and give a prelimi- the early 1990s) that it could even be achieved for pipelined se- nary overview of our group’s activities towards the demonstration quential CMOS, using their CRL [8] and SCRL [9] logic styles. of groundbreaking levels of energy efficiency for semiconductor- CRL was the first complete sequential CMOS logic family that based logic, together with a broader exploration of the ultimate is what we call truly, fully adiabatic, meaning that, in an ideal- limits of physically realizable techniques for approaching the the- ized, no-leakage limit, with negligible parasitic capacitances, the oretical ideal of perfect thermodynamic reversibility in comput- dissipation per logic operation can in principle be made arbitra- ing, and the study of the implications of this technology direction for practical computing architectures. rily small—even below Landauer’s limit of 퐸diss ≥ 푘푇 ln 2 for Keywords—Adiabatic circuits, adiabatic logic, CMOS, physical irreversible bit erasures. Due to Landauer’s Principle, we know limits of computing, low-power design, reversible computing that any physical mechanism capable of beating this limit must be logically reversible—although what that means, precisely, is misapprehended in much of the literature (see [10] for a correct This work is supported by the Advanced Simulation and Computing (ASC) account). program at the U.S. Department of Energy’s National Nuclear Security Admini- stration (NNSA). Sandia National Laboratories is a multi-mission laboratory Note that avoiding energy dissipation includes avoiding en- managed and operated by National Technology and Engineering Solutions of ergy emissions associated with side-channel attacks such as Dif- Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for ferential Power Analysis (DPA); this led to attention being paid NNSA under contract DE-NA0003525. This document describes objective to the possible security applications of adiabatic circuits and re- technical results and analysis. Any subjective views or opinions that might be versible computing as early as 2006 [11]. However, existing expressed in this document do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Approved for public implementations of adiabatic circuits typically remain far from release, SAND2020-8419 C. the reversible ideal, for several reasons that we will discuss. XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE In 2017, an effort informally termed the Adiabatic Circuits In parallel with this core engineering effort, the scope of our Feasibility Study (ACSF) began at Sandia National Laboratories effort has expanded over the last year to also include two univ- with the goal of pushing the limits of energy efficiency in ersity-based collaborations on related topics: physical implementations of adiabatic CMOS circuits, as a part of an effort to assess the long-term feasibility of these techniques 1) Karpur Shukla of Brown University is applying theoret- for possible use in future high-performance computing (HPC) ical tools from modern non-equilibrum quantum thermodyna- systems. Although the main goal of this effort is to attain more mics to derive fundamental, technology-independent lower li- power-efficient (and ultimately, more cost-efficient) computa- mits on energy dissipation as a function of delay for general tion, improving security can be a potentially beneficial side ef- quantum systems performing classical reversible computations. fect, as previously mentioned. This study may help us develop new insights into the design of innovative “Beyond CMOS” device technologies for reversible II. TECHNICAL APPROACH computing, so as to aspirationally achieve breakthrough reduc- tions in energy-delay product, and take the cost-efficient perf- As mentioned above, to avoid limiting the energy efficiency ormance of reversible computing far beyond the limits of any (i.e., to approach zero energy dissipation per operation), the phy- possible non-reversible technology. sical operation of our circuits must be truly, fully adiabatic, 2) Tom Conte and Anirudh Jain of Georgia Tech aim to which requires us to apply the principles of reversible comput- carry out a study of processor architectures based on reversible ing, albeit in the generalized sense discussed in [10]. Ignoring technology, including an assessment of the potential system- leakage for the moment, even just to approach reversible, adia- level impact of hypothetical new reversible device technologies batic operation in a switching circuit requires that the following for computational science applications. fundamental “design rules” must be obeyed [12]: 1) Avoid passing current through diodes. This is due to the III. PROGRESS TO DATE AND EARLY RESULTS “diode drop,” an intrinsic voltage drop that exists in a diode, A. Logic Family, Simulations, and Test Chip Layouts. which is unavoidable for fundamental thermodynamic reasons. As mentioned in the previous section, our approach is based 2) Avoid turning a switch (such as a FET) “on” when there on implementing truly, fully adiabatic CMOS logic styles. The is a (non-negligible) voltage difference 푉 between its drain DS first of these, historically, was Younis & Knight’s Charge Reco- and source terminals. Such an event would result in a substan- very Logic (CRL) [8]. A number of generalizations and varia- tial, non-adiabatic flow of current. tions on the techniques innovated by CRL were developed in 3) Avoid turning a switch “off” when there is a non-negli- subsequent literature (e.g., [9], [14], [15]). We selected for our gible current 퐼 between drain and source, unless these nodes DS study a version called 2LAL (two-level adiabatic logic) which is remain connected along an alternate path. The reasoning be- effectively just a slight generalization of CRL but was reinven- hind this rule is more subtle, and so it is not widely recognized, ted by one of us (Frank) in 2000. It is an attractive target for and is broken by many designs. Nevertheless, obeying this rule study because of its simple clock waveforms, which have the is essential for approaching physical reversibility [13]. shortest