AMD SP5100 Databook Technical Reference Manual Rev. 1.70 P/N: 44409_sp5100_ds_pub © 2010 Advanced Micro Devices, Inc. 42133 Trademarks AMD, the AMD Arrow logo, Opteron, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation. PCI Express is a registered trademark of PCI-SIG. USB is a registered trademark of USB Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. 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All rights reserved. Revision History Date Revision Description Oct 2010 1.70 First release of the public version. Changes from the latest released NDA version include: • Updated Table 11-3, “DC Characteristics for Interface on the SP5100”: Corrected VIL minimum value to -0.5V for CPU signals, RSMRST#, and SBPWRGD; filled in ILI values for NB-ALLOW_LDTSTP, RSMRST#, and SBPWRGD; corrected condition for GPIO/IMC_GPIO and IDE pins’ VOH to IOH=-8.0mA. • Updated Table 14-5, “List of Pins on the SP5100 XOR Chain and the Order of Connection”: Corrected pin names at XOR# 113 and 114 to USB_FSD13P and USB_FSD12P. • Updated Section 7.12, “Northbridge / Power Management Interface”: Revised description for WAKE#/GEVENT8#. • Updated Section 7.13, “SMBus Interface/General Purpose Open Controller”: Removed references to ASF, as the feature is no longer supported; SCL1/ SDA1 interface is now used as secondary SMBUS in the S5 power domain. AMD SP5100 Databook 44409 Rev. 1.70 October 10 Table of Contents 1 Introduction ............................................................................................................. 8 1.1 Features of the SP5100 ............................................................................................................. 8 1.2 Part Number and Branding ...................................................................................................... 11 2 SP5100 Block Diagram ......................................................................................... 13 3 SP5100 Power on Sequence and Timing............................................................. 14 3.1 Power Up and Down Sequences ............................................................................................. 14 4 SP5100 Strap Information ..................................................................................... 20 5 Integrated Resistor and External Pull-up/Pull-down Resistor Requirements .. 24 6 SP5100 Ballout Map .............................................................................................. 31 7 Signal Description ................................................................................................. 33 7.1 CPU Interface .......................................................................................................................... 33 7.2 LPC Interface .......................................................................................................................... 33 7.3 A-Link Express II Interface ....................................................................................................... 34 7.4 PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) ....................................................... 34 7.5 USB Interface .......................................................................................................................... 35 7.6 PATA 66/100/133 .................................................................................................................... 35 7.7 Serial ATA Interface................................................................................................................. 36 7.8 HD Audio Interface .................................................................................................................. 37 7.9 Real Time Clock Interface ........................................................................................................ 37 7.10 Hardware Monitor .................................................................................................................... 37 7.11 SPI ROM Interface .................................................................................................................. 38 7.12 Northbridge / Power Management Interface ............................................................................. 38 7.13 SMBus Interface / General Purpose Open Collector ................................................................. 40 7.14 External Event / General Event / General Power Management / General Purpose Open Collector 41 7.15 General Purpose I/O ................................................................................................................ 43 7.16 Integrated Micro-Controller (IMC) ............................................................................................. 46 7.17 Reset / Clocks / ATE ................................................................................................................ 47 7.18 Intruder Alert............................................................................................................................ 49 7.19 Power and Ground .................................................................................................................. 49 8 Functional Description ......................................................................................... 51 8.1 EHCI USB 2.0 and OHCI USB 1.1 Controllers ......................................................................... 51 8.1.1 USB Power Management ............................................................................................................... 52 8.2 SMI#/SCI Generation ............................................................................................................... 53 8.3 LPC ISA Bridge ....................................................................................................................... 54 8.3.1 LPC Interface Overview.................................................................................................................. 54 8.3.2 LPC Module Block Diagram ............................................................................................................ 56 8.4 Integrated Micro-Controller (IMC) ............................................................................................. 56 8.5 Real Time Clock ...................................................................................................................... 56 8.5.1 Functional Blocks of RTC ............................................................................................................... 57 4 Table of Contents 44409 Rev. 1.70 October 10 AMD SP5100 Databook 8.6 PATA Controller....................................................................................................................... 57 8.7 SATA (Serial ATA) Controller ................................................................................................... 57 8.8 PCI Bridge ............................................................................................................................... 58 8.9 High Definition Audio ............................................................................................................... 59 8.9.1 HD Audio Codec Connections ........................................................................................................ 59 8.10 Power management/ACPI ....................................................................................................... 59 8.11 General Events and GPIOs...................................................................................................... 59 8.12 Hardware Monitor Interface...................................................................................................... 60 9 System Clock Specifications................................................................................ 62 9.1 System Clock Descriptions and Frequency Specifications ........................................................ 62 9.2 System Clock AC Specifications .............................................................................................. 62 10 States