Europaisches Patentamt J European Patent Office © Publication number: 0 644 605 A1 Office europeen des brevets EUROPEAN PATENT APPLICATION © Application number: 94112882.9 int. CI 6: H01P 5/10 @ Date of filing: 18.08.94 © Priority: 22.09.93 US 124875 © Applicant: MOTOROLA, INC. 1303 East Algonquin Road @ Date of publication of application: Schaumburg, IL 60196 (US) 22.03.95 Bulletin 95/12 @ Inventor: Kaltenecker, Robert S. © Designated Contracting States: 2719 S. Estrella Circle DE FR GB Mesa, Arizona 85202 (US) Inventor: Pfizenmayer, Henry L. 3318 E. Turquiose Avenue Phoenix, Arizona 85028 (US) Inventor: Wernett, Frederick C. 492 Kweo Trail Flagstaff, Arizona 86001 (US) © Representative: Hudson, Peter David et al Motorola European Intellectual Property Midpoint Alencon Link Basingstoke, Hampshire RG21 1PL (GB) © Circuit and method for balun compensation. 10 © A novel circuit and method for providing am- 14 plitude and phase compensation for a balun in order P1 P2 7o,Eo | Ox to provide first and second voltage signals that are 12 1 16 balanced has been provided. The compensation is I rrm < ^ achieved by an amplitude and phase com- adding P3 pensation circuit such as a transmission line (14) or 1 mm 18 o inductive (20) and capacitive (22) lumped elements CO in series with one of the ports of the balun on the balanced side. The and amplitude phase compensa- FIG. 1 tion circuit includes a characteristic impedance CO pa- rameter (Zo) and an electrical length parameter (Eo) that are optimized such that the amplitude difference between first and second voltage signals is mini- mized, while the magnitude of the phase difference between first and second voltage signals is maxi- mized. Rank Xerox (UK) Business Services (3. 10/3.09/3.3.4) 1 EP 0 644 605 A1 2 Field of the Invention ference between first and second voltage signals is minimized. Further, the electrical length is opti- This invention relates to baluns and, in particu- mized such that the magnitude of the phase dif- lar but not limited to, a circuit and method for ference between first and second voltage signals is compensating baluns. 5 maximized. Background of the Invention Brief Description of the Drawings A balun is a well known device having a single FIG. 1 is a detailed schematic diagram illustrat- ended (unbalanced) side and a balanced side. The io ing a first embodiment of an amplitude and function of a balun is to provide voltages at first phase compensated balun in accordance with and second ports of its balanced side which are the present invention; substantially equal in amplitude and substantially FIG. 2 is a detailed schematic diagram illustrat- 180° out of phase with respect to each other. In ing a second embodiment of an amplitude and other words, the balun is to provide equal and 75 phase compensated balun in accordance with opposite voltages to a balanced load with respect the present invention; and to ground. FIG. 3 is a detailed schematic/block diagram When utilizing a balun, the balun must be utilizing the present invention to improve perfor- impedance matched with the rest of the system in mance of an amplifier. order to minimize losses and distortion and maxi- 20 mize bandwidth, for example, in balanced amplifier Detailed Description of the Drawings applications. In trying to match the balun with the system, the prior art utilizes traditional measure- Referring to FIG. 1, a detailed schematic dia- ments on the single ended side of the balun. For gram illustrating a circuit and method for providing example, in measuring the frequency response of a 25 amplitude and phase compensation for voltage sig- balun, first and second baluns are serially coupled nals appearing at first and second ports on the wherein their balanced sides are interconnected. A balanced side of balun 10 is shown. Balun 10 is signal is applied at the single ended side of the shown as a three port device having first port P1 first balun, while the signal appearing at the single coupled to terminal 12, second port P2 coupled ended side of the second balun is observed. From 30 through amplitude and phase compensation circuit this measurement, one can obtain the bandwidth, 14 to terminal 16. Further, balun 10 includes third insertion loss and return loss for each balun (as- port P3 coupled to terminal 18. It is understood that suming that each balun is substantially identical). port P1 is on the single ended side of balun 10, However, these measurements do not convey any while ports P2 and P3 are on the balanced side of information about the amplitude and phase relation- 35 balun 10. Further, it is understood that balun 10 ships appearing at the balanced side of the balun. includes three twisted wires wherein a first wire has Hence, there exists a need for recognizing that a first end coupled to port P1 and a second end the amplitude and phase of the voltage signals coupled to a first end of a second wire and to port appearing at the balanced side of a balun may P2. Further, the second end of the second wire is degrade with frequency and for further providing a 40 coupled to a first end of a third wire, while the circuit and method for providing compensation for second end of the third wire is coupled to port P3. such amplitude and phase degradation. In general, if an input signal is applied at termi- nal 12 (and hence to port P1), then ideally ports P2 Summary of the Invention and P3 of balun 10 should provide equal amplitude 45 voltage signals that are substantially 180° out of Briefly, the present invention provides a circuit phase and wherein the amplitude of these voltage and a method for amplitude and phase compensat- signals is substantially equal to one-half the am- ing first and second voltages appearing at the plitude of the voltage signal applied terminal 12 balanced side of a balun. The present invention (less any loss through balun 10 as is understood). first realizes that the amplitude and phase of the 50 The present invention realizes that as the fre- voltages appearing at the balanced side of a balun quency of operation of balun 10 increases, the do indeed degrade with frequency. Further, the voltage signals appearing at ports P2 and P3 de- present invention provides an amplitude and phase grade with respect to frequency. That is, as the compensation circuit having a predetermined op- frequency increases, the amplitude difference be- timized electrical length and characteristic imped- 55 tween the voltage signals appearing at ports P2 ance that is inserted in series with a port on the and P3 increases, while the phase difference be- balanced side of the balun. The characteristic im- tween the voltage signals appearing at ports P2 pedance is optimized such that the amplitude dif- and P3 are no longer substantially 180° out of 2 3 EP 0 644 605 A1 4 phase with respect to each other. Although FIG. 1 shows transmission line 14 Moreover, the present invention then realizes being utilized to provide the amplitude in phase that by inserting an amplitude and phase com- compensation, it is understood that a combination pensation circuit such as transmission line 14 in of lumped inductive and capacitive components series with port P2, the amplitude and phase of 5 having selected characteristic impedance and elec- first and second voltage signals respectively ap- trical length could also be utilized as shown in FIG. pearing at terminals 16 and 18 can be compen- 2. In particular, FIG. 2 illustrates the amplitude and sated with respect to frequency. In particular, by phase compensation circuit to include inductor 20 appropriately selecting optimized values for the and capacitor 22 wherein inductor 20 is coupled characteristic impedance (Zo) and the electrical io between the second port of balun 10 and terminal length (Eo) of transmission line 14, the amplitude 16 while capacitor 22 is coupled between port P2 difference between the first and second voltage and ground reference. Moreover, it should be un- signals can be minimized, while the magnitude of derstood that other variations of lumped compo- the phase difference between the first and second nents may also be utilized such as including an voltage signals can be maximized. By maximizing is additional capacitor coupled between terminal 16 the magnitude of the phase difference between the and ground reference. first and second voltage signals, it is intended to Referring to FIG. 3, a detailed schematic/block mean that the phase difference between the first diagram utilizing the circuit shown in FIG. 1 to and second voltage signals is made substantially improve performance of an amplifier is shown. It is equal to 180°. In this manner, the first and second 20 understood that components shown in FIG. 3 that voltage signals provided at terminals 16 and 18 are are identical to components shown in FIG. 1 are said to be balanced. identified by the same reference numbers. For In order to optimize the values for the char- example, baluns 10' and 10" of FIG. 3 are the acteristic impedance and the electrical length of same as balun 10 of FIG. 1. Moreover, transmis- transmission line 14, any RF linear analysis pro- 25 sion lines 14' and 14" of FIG. 3 are identical to gram capable of handling distributed elements may transmission line 14 of FIG. 1. be utilized such as Hewlett Packard's Microwave The circuit shown in FIG. 3 further includes Design System (MDS) or Touchstone. For exam- amplifier 30, for example, a cable television (CATV) ple, by taking three port measurements at ports P1 , amplifier, having balanced inputs and outputs.