Amorphous silicon thin-film transistors for flexible electronics Helena Gleskova, I-Chun Cheng, Ke Long, Sigurd Wagner, James Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials Princeton University Zhigang Suo Division of Engineering and Applied Sciences, Harvard University The work at Princeton University is supported by the United States Display Consortium. Berkeley, April 13, 2007 Flexible displays Lucent, E-Ink http://www.eink.com/iim/sale.html Transistor “backplane” and display “frontplane” Schematic cross section Amorphous silicon thin film transistor of a display generic backplane Gate Source Drain Encapsulation 1 μm - 1 mm Cr a-Si:H Display layer (LCD, PLED..) SiNx Transistor layer ~ 1 μm Passivation layer Substrate Substrate: glass, steel, plastic 10 μm - 1 mm Backplane | Frontplane Passivation layer • TFT backplane is generic for all flat panel technologies • Add display layer on top Gleskova H., Wagner S., IEEE Electron Device Letters 20 (1999), pp. 473-475. Outline • Metal versus plastic foil substrate • a-Si:H TFT deposition temperature • Overlay alignment Steel versus plastic Cheng I-C. et al., IEEE EDL 27 (2006) 166. Kattamis A.Z., Princeton University polymer foil substrate steel foil substrate < 280°C process temperature up to ~1000°C low dimensional stability > 10 times higher some visually clear no yes permeable to O2 or H2O no moderate surface roughness rough some inert to chemicals yes no electrical conductor yes Steel versus plastic Cheng I-C. et al., IEEE EDL 27 (2006) 166. Kattamis A.Z., Princeton University polymer foil substrate steel foil substrate < 280°C process temperature up to ~1000°C low dimensional stability > 10 times higher some visually clear no yes permeable to O2 or H2O no moderate surface roughness rough some inert to chemicals yes no electrical conductor yes a-Si:H TFTs made at 150ºC on Kapton Gate-to-source current current Gate-to-source I -5 Tdep = 150ºC Vds = 10 V -5 (A) 10 10 ds 0.1 V 10-7 10-7 Gate Source Drain I 10-9 ds 10-9 -11 Igs -11 10 10 gs (A) Drain-to-source current current I Drain-to-source 10-13 10-13 -10 -5 0 5 10 15 20 Gate-to-source voltage Vgs (V) 7 2 Ion/Ioff > 10 , μlin ~ 0.45 cm /Vs, VT ~ 2 V Acceptable TFT performance, but … Gleskova H. et al., J. Electrochem. Society 148 (2001), pp. G370-G374. Gleskova H. et al., J. Appl. Phys. 92 (2002), pp. 6224-6229. Bias-stress instability of a-Si:H TFTs 10-4 10-5 Stress time: 600 sec 10-6 (A) D 10-7 10-8 Initial After stress of 10-9 Vg = 20 V Drain Current I 10-10 10-11 10-12 -10 -5 0 5 10 15 20 Gate-to-Source Voltage V (V) GS Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113. a-Si TFT stability rises with process temperature Glass (300°C-350°C) [2] Kapton-E (150°C) [1] 10 [1] Gleskova, IEEE TED, (V) Τ 2001 V Δ Glass (150°C) [5] [2] Cheng, IEEE Proc. Solid-State and Integrated Circuit Tech., 1998 1 Glass (350°C) [3] [3] Kanicki, APL, 1993 [4] Tsukada, JAP, 1991 Stress time: Threshold Change 600sec Glass (300°C-360°C) [4] [5] Long, Princeton Univ. 0.1 10 Stress Field (*107 V/m) ⇒ Must make a-Si:H TFTs at high process temperature a-Si:H TFTs made on clear plastic at 280ºC Cherenack K., Princeton University a-Si:H TFT stability on clear plastic substrates Kapton-E (150°C) Glass (300°C-350°C) 10 (V) Glass (150°C) Τ V Δ Clear plastic (150ºC) 1 Glass (350°C) Glass (300°C-360°C) Threshold Change 0.1 Stress time: 600sec Clear Plastic (250ºC) 10 Stress Field (*107 V/m) ΔVT depends only on process T, not on substrate material Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113. Steel versus plastic Cheng I-C. et al., IEEE EDL 27 (2006) 166. Kattamis A.Z., Princeton University polymer foil substrate steel foil substrate < 280°C process temperature up to ~1000°C low dimensional stability > 10 times higher some visually clear no yes permeable to O2 or H2O no moderate surface roughness rough some inert to chemicals yes no electrical conductor yes Substrate stiffness affects dimensional stability thin film (small df) Ys⋅ds versus Yf ⋅df stiff (large Yf) compliant (small Yf) poly-Si TFT / steel substrate OLED / steel substrate Wu M. et al., APL 75 (1999) 2244 Wu C.C. et al., IEEE EDL 18 (1997) 609 stiff (large Ys) thick Ys⋅ds >> Yf ⋅df Y ⋅d >> Y ⋅d substrate s s f f (large ds) a-Si TFT / polymer substrate OTFT / polymer substrate Gleskova H., Princeton University Jackson T., Penn State Univ. compliant (small Ys) Ys⋅ds ≈ Yf ⋅df Ys⋅ds >> Yf ⋅df a-Si:H TFT process 1. Front SiNx passivation 2. Back SiN passivation 80 nm x SiNx Kapton 500 nm 3. Cr gate metal deposition 4. Cr gate patterning - mask 1 Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. a-Si:H TFT process – cont. (n+) a-Si:H Cr 80 nm undoped 50 nm a-Si:H 200 nm 300 nm SiNx Substrate 5. PECVD TFT stack: 5 W SiNx 5. PECVD TFT stack: 12 W SiNx (i) a-Si:H (i) a-Si:H (n+) a-Si:H (n+) a-Si:H 6. Cr S/D deposition 6. Cr S/D deposition 7. S/D patterning – mask 2 7. S/D patterning – mask 2 Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Location of alignment marks 70 mm 52 mm 70 mm 1 2 52 mm 5 roll axis feature of mask 1: bottom gate metal layer 3 4 mask 1 & 2 40 μm feature of mask 2: S/D layer Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. 2 1 5W gate SiNx ~ 52 mm shrinkage ~ 30 μm 5 40 μm 40 μm ~ 52 mm shrink. ~ 25 μm shrink. ~ 20 μm ~ 52 mm 3 4 40 μm shrinkage ~ 28 μm ~ 52 mm 40 μm 40 μm Average shrinkage ~ 500 ppm Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. 1 2 12W gate SiNx ~ 52 mm stretching ~ 6 μm 5 40 μm 40 μm ~ 52 mm shrink. ~ 10 μm shrink. ~ 1 μm ~ 52 mm 3 4 40 μm 40 μm stretching ~ 3 μm ~ 52 mm 40 μm 40 μm Average change ~ 100 ppm Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Film grown on foil substrate at elevated temperature Substrate at room αs (Td –Tr ) temperature Tr Substrate at deposition temperature Td εs(Td ) Free-standing film at Td εbi εbi < 0 εf (Td ) Workpiece at Td after film growth αs > αf αf (Td –Tr ) Film and substrate at Tr if they were separated εf (Tr ) Workpiece at Tr when held flat εs(Tr ) [(α f − α s )⋅ (Tr − Td )+ εbi ] ε (T ) = ν =ν s r Y d f s 1+ s s Y f d f Gleskova H. et al., in Flexible Electronics: Materials and Applications, Gleskova H. et al., Appl. Phys. Lett. 88 (2006), 011905. Eds. Wong W.S., Salleo A., Springer-Verlag – to be published. Film release from the substrate holder Workpiece at Tr when held flat Workpiece at Tr when released from the substrate holder SiNx R Bare8 19 24 40 mW/cm2 2 ⎛ 2 ⎞ 2 ⎜ Y f d f ⎟ Y f d f ⎛ d f ⎞ 1− + 4 ⎜1+ ⎟ ⎜ 2 ⎟ Y d ⎜ d ⎟ d ⎜ Ysds ⎟ s s ⎝ s ⎠ R = s ⋅ ⎝ ⎠ Y f d f ⎛ d f ⎞ 6 ()1+ν []()α f −αs ⋅()Tr −Td +ε bi ⎜1+ ⎟ Ysds ⎝ ds ⎠ Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Suo Z. et al., Appl. Phys. Lett. 74 (1999), pp. 1177-1179. Steel foil 0.1 60 after film deposition ) Td 40 -1 o Substrate strain 0.05 250 C ε o s 200 C 20 (T o r Steel 150 C (ppm)) 0 0 -20 -0.05 compressive tensile -40 Curvature 1/R (cm 1/R Curvature built-in stress built-in stress -0.1 -60 0.01 0.005 0 -0.005 -0.01 SiNx built-in strain A rigid substrate foil is not changed much by CTE mismatch Possible to maintain reasonable overlay accuracy Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published. Kapton foil 1 1000 after film deposition ) Td -1 o Substrate strain 0.5 250 C 500 ε o s 200 C (T o r Kapton 150 C (ppm)) 0 0 -0.5 -500 compressive tensile Curvature 1/R (cmCurvature built-in stress built-in stress -1 -1000 0.01 0.005 0 -0.005 -0.01 SiNx built-in strain Stress built into the SiNx can compensate thermal mismatch and eliminate curvature and misalignment Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published. Summary • Higher deposition temperatures needed for good TFT stability • Deposition at elevated temperature changes in-plane dimensions d f d f • Changes are small if <~ 0 . 05 (steel) or <~ 0 . 001 (Kapton) ds ds • CTE mismatch change in in-plane dimensions is ~ 20 ppm for a-Si:H TFTs on 100-μm steel foil ~ 500 ppm for a-Si:H TFTs on 100-μm Kapton foil • Tailor built-in stress in the film to compensate CTE mismatch ⇒ possible to eliminate misalignment ⇒ possible to eliminate curvature of the workpiece.